target/cortex_m: enhance multi-core examine logs

[fw/openocd] / src / target / armv7a.h

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 9b1436c723a86732694c6d8fb4d70f691afc3b76..c282554a5ea6a4b7385102687ba61b81babe6cb9 100644 (file)
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -48,7 +48,7 @@ struct armv7a_l2x_cache {
 };
 
 struct armv7a_cachesize {
-       /*  cache dimensionning */
+       /*  cache dimensioning */
        uint32_t linelen;
        uint32_t associativity;
        uint32_t nsets;
@@ -104,7 +104,7 @@ struct armv7a_common {
 
        /* Core Debug Unit */
        struct arm_dpm dpm;
-       uint32_t debug_base;
+       target_addr_t debug_base;
        struct adiv5_ap *debug_ap;
        /* mdir */
        uint8_t multi_processor_system;
@@ -178,6 +178,9 @@ static inline bool is_armv7a(struct armv7a_common *armv7a)
 /* See ARMv7a arch spec section C10.8 */
 #define CPUDBG_AUTHSTATUS      0xFB8
 
+/* See ARMv7a arch spec DDI 0406C C11.10 */
+#define CPUDBG_ID_PFR1         0xD24
+
 /* Masks for Vector Catch register */
 #define DBG_VCR_FIQ_MASK       ((1 << 31) | (1 << 7))
 #define DBG_VCR_IRQ_MASK       ((1 << 30) | (1 << 6))
@@ -192,7 +195,7 @@ int armv7a_arch_state(struct target *target);
 int armv7a_identify_cache(struct target *target);
 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
 
-int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv7a_handle_cache_info_command(struct command_invocation *cmd,
                struct armv7a_cache_common *armv7a_cache);
 int armv7a_read_ttbcr(struct target *target);