cortex_m: Select an AP when accessing the DAP

[fw/openocd] / src / target / armv7a.h

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 6a614a18305154467a9d0d4f9873f81026ecb138..a71aa23c7b2bbd5113be28816ad4ff5dcfc87c09 100644 (file)
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -21,6 +21,7 @@
 #define ARMV7A_H
 
 #include "arm_adi_v5.h"
+#include "armv7a_cache.h"
 #include "arm.h"
 #include "armv4_5_mmu.h"
 #include "armv4_5_cache.h"
@@ -62,17 +63,27 @@ struct armv7a_cachesize {
        uint32_t way_shift;
 };
 
-struct armv7a_cache_common {
-       int ctype;
+/* information about one architecture cache at any level */
+struct armv7a_arch_cache {
+       int ctype;                              /* cache type, CLIDR encoding */
        struct armv7a_cachesize d_u_size;       /* data cache */
        struct armv7a_cachesize i_size;         /* instruction cache */
+};
+
+/* common cache information */
+struct armv7a_cache_common {
+       int info;                               /* -1 invalid, else valid */
+       int loc;                                /* level of coherency */
+       uint32_t dminline;                      /* minimum d-cache linelen */
+       uint32_t iminline;                      /* minimum i-cache linelen */
+       struct armv7a_arch_cache arch[6];       /* cache info, L1 - L7 */
        int i_cache_enabled;
        int d_u_cache_enabled;
-       /* l2 external unified cache if some */
-       void *l2_cache;
+       int auto_cache_enabled;                 /* openocd automatic
+                                                * cache handling */
+       /* outer unified cache if some */
+       void *outer_cache;
        int (*flush_all_data_cache)(struct target *target);
-       int (*display_cache_info)(struct command_context *cmd_ctx,
-                       struct armv7a_cache_common *armv7a_cache);
 };
 
 struct armv7a_mmu_common {
@@ -81,7 +92,6 @@ struct armv7a_mmu_common {
        uint32_t ttbcr;     /* cache for ttbcr register */
        uint32_t ttbr_mask[2];
        uint32_t ttbr_range[2];
-       uint32_t os_border;
 
        int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size,
                        uint32_t count, uint8_t *buffer);
@@ -161,6 +171,7 @@ target_to_armv7a(struct target *target)
 
 /* See ARMv7a arch spec section C10.7 */
 #define CPUDBG_DSCCR           0x028
+#define CPUDBG_DSMCR           0x02C
 
 /* See ARMv7a arch spec section C10.8 */
 #define CPUDBG_AUTHSTATUS      0xFB8