};
struct armv7a_cachesize {
- /* cache dimensionning */
+ /* cache dimensioning */
uint32_t linelen;
uint32_t associativity;
uint32_t nsets;
/* following field mmu working way */
int32_t cached; /* 0: not initialized, 1: initialized */
uint32_t ttbcr; /* cache for ttbcr register */
+ uint32_t ttbr[2];
uint32_t ttbr_mask[2];
uint32_t ttbr_range[2];
- int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size,
+ int (*read_physical_memory)(struct target *target, target_addr_t address, uint32_t size,
uint32_t count, uint8_t *buffer);
struct armv7a_cache_common armv7a_cache;
uint32_t mmu_enabled;
struct arm_dpm dpm;
uint32_t debug_base;
struct adiv5_ap *debug_ap;
- struct adiv5_ap *memory_ap;
- bool memory_ap_available;
/* mdir */
uint8_t multi_processor_system;
+ uint8_t multi_threading_processor;
+ uint8_t level2_id;
uint8_t cluster_id;
uint8_t cpu_id;
bool is_armv7r;
/* See ARMv7a arch spec section C10.8 */
#define CPUDBG_AUTHSTATUS 0xFB8
+/* See ARMv7a arch spec DDI 0406C C11.10 */
+#define CPUDBG_ID_PFR1 0xD24
+
/* Masks for Vector Catch register */
#define DBG_VCR_FIQ_MASK ((1 << 31) | (1 << 7))
#define DBG_VCR_IRQ_MASK ((1 << 30) | (1 << 6))
#define DBG_VCR_PREF_ABORT_MASK ((1 << 27) | (1 << 3))
#define DBG_VCR_SVC_MASK ((1 << 26) | (1 << 2))
+/* Masks for Multiprocessor Affinity Register */
+#define MPIDR_MP_EXT (1UL << 31)
+
int armv7a_arch_state(struct target *target);
int armv7a_identify_cache(struct target *target);
int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
-int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
- uint32_t *val, int meminfo);
-int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val);
-int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv7a_handle_cache_info_command(struct command_invocation *cmd,
struct armv7a_cache_common *armv7a_cache);
+int armv7a_read_ttbcr(struct target *target);
extern const struct command_registration armv7a_command_handlers[];