/* Cache and Memory Management Unit */
armv4_5_mmu_common_t armv4_5_mmu;
armv4_5_common_t armv4_5_common;
- void *arch_info;
// int (*full_context)(struct target_s *target);
// int (*read_core_reg)(struct target_s *target, int num, enum armv7a_mode mode);
uint32_t CRn, uint32_t CRm, uint32_t value);
int (*examine_debug_reason)(target_t *target);
- void (*pre_debug_entry)(target_t *target);
void (*post_debug_entry)(target_t *target);
void (*pre_restore_context)(target_t *target);
} armv7a_common_t;
+static inline struct armv7a_common_s *
+target_to_armv7a(struct target_s *target)
+{
+ return container_of(target->arch_info, struct armv7a_common_s,
+ armv4_5_common);
+}
+
typedef struct armv7a_algorithm_s
{
int common_magic;