target: change prototype of handle_bp_command_set()

[fw/openocd] / src / target / armv7a.h

diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 14112e4ed0267958f2ce392f0044e2dbf83b9078..0ef04c162abf36fbb684a6b508f75bb9641b4c56 100644 (file)
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -87,6 +87,7 @@ struct armv7a_mmu_common {
        /* following field mmu working way */
        int32_t cached;     /* 0: not initialized, 1: initialized */
        uint32_t ttbcr;     /* cache for ttbcr register */
+       uint32_t ttbr[2];
        uint32_t ttbr_mask[2];
        uint32_t ttbr_range[2];
 
@@ -105,10 +106,10 @@ struct armv7a_common {
        struct arm_dpm dpm;
        uint32_t debug_base;
        struct adiv5_ap *debug_ap;
-       struct adiv5_ap *memory_ap;
-       bool memory_ap_available;
        /* mdir */
        uint8_t multi_processor_system;
+       uint8_t multi_threading_processor;
+       uint8_t level2_id;
        uint8_t cluster_id;
        uint8_t cpu_id;
        bool is_armv7r;
@@ -184,15 +185,16 @@ static inline bool is_armv7a(struct armv7a_common *armv7a)
 #define DBG_VCR_PREF_ABORT_MASK        ((1 << 27) | (1 << 3))
 #define DBG_VCR_SVC_MASK       ((1 << 26) | (1 << 2))
 
+/* Masks for Multiprocessor Affinity Register */
+#define MPIDR_MP_EXT           (1UL << 31)
+
 int armv7a_arch_state(struct target *target);
 int armv7a_identify_cache(struct target *target);
 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
-int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
-               uint32_t *val, int meminfo);
-int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val);
 
-int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv7a_handle_cache_info_command(struct command_invocation *cmd,
                struct armv7a_cache_common *armv7a_cache);
+int armv7a_read_ttbcr(struct target *target);
 
 extern const struct command_registration armv7a_command_handlers[];