{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm_dpm *dpm = armv7a->arm.dpm;
- uint32_t ttbcr;
- uint32_t ttbr0, ttbr1;
+ uint32_t ttbcr, ttbcr_n;
int retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
goto done;
if (retval != ERROR_OK)
goto done;
- retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 0, 0, 2, 0, 0),
- &ttbr0);
- if (retval != ERROR_OK)
- goto done;
-
- retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 0, 0, 2, 0, 1),
- &ttbr1);
- if (retval != ERROR_OK)
- goto done;
+ LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
- LOG_INFO("ttbcr %" PRIx32 "ttbr0 %" PRIx32 "ttbr1 %" PRIx32, ttbcr, ttbr0, ttbr1);
+ ttbcr_n = ttbcr & 0x7;
+ armv7a->armv7a_mmu.ttbcr = ttbcr;
+ armv7a->armv7a_mmu.cached = 1;
- armv7a->armv7a_mmu.ttbr1_used = ((ttbcr & 0x7) != 0) ? 1 : 0;
- armv7a->armv7a_mmu.ttbr0_mask = 0;
+ /*
+ * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
+ * document # ARM DDI 0406C
+ */
+ armv7a->armv7a_mmu.ttbr_range[0] = 0xffffffff >> ttbcr_n;
+ armv7a->armv7a_mmu.ttbr_range[1] = 0xffffffff;
+ armv7a->armv7a_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
+ armv7a->armv7a_mmu.ttbr_mask[1] = 0xffffffff << 14;
+ armv7a->armv7a_mmu.cached = 1;
retval = armv7a_read_midr(target);
if (retval != ERROR_OK)
goto done;
- if (armv7a->partnum & 0xf) {
- /*
- * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
- * document # ARM DDI 0406C
- */
- armv7a->armv7a_mmu.ttbr0_mask = 1 << (14 - ((ttbcr & 0x7)));
- } else {
+ /* FIXME: why this special case based on part number? */
+ if ((armv7a->partnum & 0xf) == 0) {
/* ARM DDI 0344H , ARM DDI 0407F */
- armv7a->armv7a_mmu.ttbr0_mask = 7 << (32 - ((ttbcr & 0x7)));
- /* fix me , default is hard coded LINUX border */
- armv7a->armv7a_mmu.os_border = 0xc0000000;
+ armv7a->armv7a_mmu.ttbr_mask[0] = 7 << (32 - ttbcr_n);
}
- LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32,
- armv7a->armv7a_mmu.ttbr1_used ? "used" : "not used",
- armv7a->armv7a_mmu.ttbr0_mask);
+ LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
+ (ttbcr_n != 0) ? "used" : "not used",
+ armv7a->armv7a_mmu.ttbr_mask[0],
+ armv7a->armv7a_mmu.ttbr_mask[1]);
- if (armv7a->armv7a_mmu.ttbr1_used == 1) {
+ /* FIXME: default is hard coded LINUX border */
+ armv7a->armv7a_mmu.os_border = 0xc0000000;
+ if (ttbcr_n != 0) {
LOG_INFO("SVC access above %" PRIx32,
- (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask));
- armv7a->armv7a_mmu.os_border = 0xffffffff & armv7a->armv7a_mmu.ttbr0_mask;
+ armv7a->armv7a_mmu.ttbr_range[0] + 1);
+ armv7a->armv7a_mmu.os_border = armv7a->armv7a_mmu.ttbr_range[0] + 1;
}
done:
dpm->finish(dpm);
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm_dpm *dpm = armv7a->arm.dpm;
- uint32_t ttb = 0; /* default ttb0 */
- if (armv7a->armv7a_mmu.ttbr1_used == -1)
- armv7a_read_ttbcr(target);
- if ((armv7a->armv7a_mmu.ttbr1_used) &&
- (va > (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask))) {
- /* select ttb 1 */
- ttb = 1;
- }
+ uint32_t ttbidx = 0; /* default to ttbr0 */
+ uint32_t ttb_mask;
+ uint32_t va_mask;
+ uint32_t ttbcr;
+ uint32_t ttb;
+
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
goto done;
- /* MRC p15,0,<Rt>,c2,c0,ttb */
+ /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(15, 0, 0, 2, 0, ttb),
+ ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
+ &ttbcr);
+ if (retval != ERROR_OK)
+ goto done;
+
+ /* if ttbcr has changed or was not read before, re-read the information */
+ if ((armv7a->armv7a_mmu.cached == 0) ||
+ (armv7a->armv7a_mmu.ttbcr != ttbcr)) {
+ armv7a_read_ttbcr(target);
+ }
+
+ /* if va is above the range handled by ttbr0, select ttbr1 */
+ if (va > armv7a->armv7a_mmu.ttbr_range[0]) {
+ /* select ttb 1 */
+ ttbidx = 1;
+ }
+ /* MRC p15,0,<Rt>,c2,c0,ttbidx */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 2, 0, ttbidx),
&ttb);
if (retval != ERROR_OK)
return retval;
+
+ ttb_mask = armv7a->armv7a_mmu.ttbr_mask[ttbidx];
+ va_mask = 0xfff00000 & armv7a->armv7a_mmu.ttbr_range[ttbidx];
+
+ LOG_DEBUG("ttb_mask %" PRIx32 " va_mask %" PRIx32 " ttbidx %i",
+ ttb_mask, va_mask, ttbidx);
retval = armv7a->armv7a_mmu.read_physical_memory(target,
- (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
+ (ttb & ttb_mask) | ((va & va_mask) >> 18),
4, 1, (uint8_t *)&first_lvl_descriptor);
if (retval != ERROR_OK)
return retval;
}
- if ((first_lvl_descriptor & 0x3) == 2) {
+ if ((first_lvl_descriptor & 0x40002) == 2) {
/* section descriptor */
*val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
return ERROR_OK;
+ } else if ((first_lvl_descriptor & 0x40002) == 0x40002) {
+ /* supersection descriptor */
+ if (first_lvl_descriptor & 0x00f001e0) {
+ LOG_ERROR("Physical address does not fit into 32 bits");
+ return ERROR_TARGET_TRANSLATION_FAULT;
+ }
+ *val = (first_lvl_descriptor & 0xff000000) | (va & 0x00ffffff);
+ return ERROR_OK;
}
- if ((first_lvl_descriptor & 0x3) == 1) {
- /* coarse page table */
- retval = armv7a->armv7a_mmu.read_physical_memory(target,
- (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
- 4, 1, (uint8_t *)&second_lvl_descriptor);
- if (retval != ERROR_OK)
- return retval;
- } else if ((first_lvl_descriptor & 0x3) == 3) {
- /* fine page table */
- retval = armv7a->armv7a_mmu.read_physical_memory(target,
- (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
- 4, 1, (uint8_t *)&second_lvl_descriptor);
- if (retval != ERROR_OK)
- return retval;
- }
+ /* page table */
+ retval = armv7a->armv7a_mmu.read_physical_memory(target,
+ (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
+ 4, 1, (uint8_t *)&second_lvl_descriptor);
+ if (retval != ERROR_OK)
+ return retval;
second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
&second_lvl_descriptor);
if ((second_lvl_descriptor & 0x3) == 1) {
/* large page descriptor */
*val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
- return ERROR_OK;
- }
-
- if ((second_lvl_descriptor & 0x3) == 2) {
+ } else {
/* small page descriptor */
*val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
- return ERROR_OK;
}
- if ((second_lvl_descriptor & 0x3) == 3) {
- *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
- return ERROR_OK;
- }
-
- /* should not happen */
- LOG_ERROR("Address translation failure");
- return ERROR_TARGET_TRANSLATION_FAULT;
+ return ERROR_OK;
done:
return retval;
return ERROR_OK;
}
-static int _armv7a_flush_all_data(struct target *target)
-{
- struct armv7a_common *armv7a = target_to_armv7a(target);
- struct arm_dpm *dpm = armv7a->arm.dpm;
- struct armv7a_cachesize *d_u_size =
- &(armv7a->armv7a_mmu.armv7a_cache.d_u_size);
- int32_t c_way, c_index = d_u_size->index;
- int retval;
- /* check that cache data is on at target halt */
- if (!armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) {
- LOG_INFO("flushed not performed :cache not on at target halt");
- return ERROR_OK;
- }
- retval = dpm->prepare(dpm);
- if (retval != ERROR_OK)
- goto done;
- do {
- c_way = d_u_size->way;
- do {
- uint32_t value = (c_index << d_u_size->index_shift)
- | (c_way << d_u_size->way_shift);
- /* DCCISW */
- /* LOG_INFO ("%d %d %x",c_way,c_index,value); */
- retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
- value);
- if (retval != ERROR_OK)
- goto done;
- c_way -= 1;
- } while (c_way >= 0);
- c_index -= 1;
- } while (c_index >= 0);
- return retval;
-done:
- LOG_ERROR("flushed failed");
- dpm->finish(dpm);
- return retval;
-}
-
-static int armv7a_flush_all_data(struct target *target)
-{
- int retval = ERROR_FAIL;
- /* check that armv7a_cache is correctly identify */
- struct armv7a_common *armv7a = target_to_armv7a(target);
- if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1) {
- LOG_ERROR("trying to flush un-identified cache");
- return retval;
- }
-
- if (target->smp) {
- /* look if all the other target have been flushed in order to flush level
- * 2 */
- struct target_list *head;
- struct target *curr;
- head = target->head;
- while (head != (struct target_list *)NULL) {
- curr = head->target;
- if (curr->state == TARGET_HALTED) {
- LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid);
- retval = _armv7a_flush_all_data(curr);
- }
- head = head->next;
- }
- } else
- retval = _armv7a_flush_all_data(target);
- return retval;
-}
-
/* L2 is not specific to armv7a a specific file is needed */
static int armv7a_l2x_flush_all_data(struct target *target)
{
uint32_t base = l2x_cache->base;
uint32_t l2_way = l2x_cache->way;
uint32_t l2_way_val = (1 << l2_way) - 1;
- retval = armv7a_flush_all_data(target);
+ retval = armv7a_cache_auto_flush_all_data(target);
if (retval != ERROR_OK)
return retval;
retval = target->type->write_phys_memory(target,
return ERROR_OK;
}
-
+/* FIXME: remove it */
static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
{
struct armv7a_l2x_cache *l2x_cache;
return JIM_OK;
}
+/* FIXME: remove it */
COMMAND_HANDLER(handle_cache_l2x)
{
struct target *target = get_current_target(CMD_CTX);
int retval = ERROR_FAIL;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm_dpm *dpm = armv7a->arm.dpm;
- uint32_t cache_selected, clidr;
+ uint32_t cache_selected, clidr, ctr;
uint32_t cache_i_reg, cache_d_reg;
struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache);
if (!armv7a->is_armv7r)
armv7a_read_ttbcr(target);
retval = dpm->prepare(dpm);
+ if (retval != ERROR_OK)
+ goto done;
+ /* retrieve CTR
+ * mrc p15, 0, r0, c0, c0, 1 @ read ctr */
+ retval = dpm->instr_read_data_r0(dpm,
+ ARMV4_5_MRC(15, 0, 0, 0, 0, 1),
+ &ctr);
if (retval != ERROR_OK)
goto done;
+
+ cache->iminline = 4UL << (ctr & 0xf);
+ cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
+ LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32,
+ ctr, cache->iminline, cache->dminline);
+
/* retrieve CLIDR
* mrc p15, 1, r0, c0, c0, 1 @ read clidr */
retval = dpm->instr_read_data_r0(dpm,
armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
armv7a_handle_inner_cache_info_command;
armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
- armv7a_flush_all_data;
+ armv7a_cache_auto_flush_all_data;
}
armv7a->armv7a_mmu.armv7a_cache.ctype = 0;
armv7a->armv7a_mmu.armv7a_cache.ctype = -1;
armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL;
armv7a->armv7a_mmu.armv7a_cache.display_cache_info = NULL;
+ armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled = 1;
return ERROR_OK;
}
COMMAND_REGISTRATION_DONE
};
-
const struct command_registration armv7a_command_handlers[] = {
{
.chain = dap_command_handlers,
{
.chain = l2x_cache_command_handlers,
},
+ {
+ .chain = arm7a_cache_command_handlers,
+ },
COMMAND_REGISTRATION_DONE
};
projects / fw / openocd / blobdiff