adi_v5_cmsis_dap.c: Simplify debugging output

[fw/openocd] / src / target / armv7a.c

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 6a41e0dbd375639e3568800fcb57841cabaa27a8..bf474d3a62f5ad30e1dba95e02ab749bf2829cec 100644 (file)
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -468,7 +468,7 @@ static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t
        l2x_cache->base,l2x_cache->way);*/
        if (armv7a->armv7a_mmu.armv7a_cache.l2_cache)
                LOG_INFO("cache l2 already initialized\n");
-       armv7a->armv7a_mmu.armv7a_cache.l2_cache = (void *) l2x_cache;
+       armv7a->armv7a_mmu.armv7a_cache.l2_cache = l2x_cache;
        /*  initialize l1 / l2x cache function  */
        armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache
                = armv7a_l2x_flush_all_data;
@@ -482,7 +482,7 @@ static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t
                        armv7a = target_to_armv7a(curr);
                        if (armv7a->armv7a_mmu.armv7a_cache.l2_cache)
                                LOG_ERROR("smp target : cache l2 already initialized\n");
-                       armv7a->armv7a_mmu.armv7a_cache.l2_cache = (void *) l2x_cache;
+                       armv7a->armv7a_mmu.armv7a_cache.l2_cache = l2x_cache;
                        armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
                                armv7a_l2x_flush_all_data;
                        armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
@@ -545,6 +545,16 @@ static int armv7a_read_mpidr(struct target *target)
                        &mpidr);
        if (retval != ERROR_OK)
                goto done;
+
+       /* ARMv7R uses a different format for MPIDR.
+        * When configured uniprocessor (most R cores) it reads as 0.
+        * This will need to be implemented for multiprocessor ARMv7R cores. */
+       if (armv7a->is_armv7r) {
+               if (mpidr)
+                       LOG_ERROR("MPIDR nonzero in ARMv7-R target");
+               goto done;
+       }
+
        if (mpidr & 1<<31) {
                armv7a->multi_processor_system = (mpidr >> 30) & 1;
                armv7a->cluster_id = (mpidr >> 8) & 0xf;
@@ -555,7 +565,7 @@ static int armv7a_read_mpidr(struct target *target)
                        armv7a->multi_processor_system == 0 ? "multi core" : "mono core");
 
        } else
-               LOG_ERROR("mpdir not in multiprocessor format");
+               LOG_ERROR("MPIDR not in multiprocessor format");
 
 done:
        dpm->finish(dpm);
@@ -785,7 +795,7 @@ const struct command_registration l2x_cache_command_handlers[] = {
        {
                .name = "cache_config",
                .mode = COMMAND_EXEC,
-               .help = "cache configuation for a target",
+               .help = "cache configuration for a target",
                .usage = "",
                .chain = l2_cache_commands,
        },