change #include "armv4_5.h" to <target/armv4_5.h>

[fw/openocd] / src / target / armv7a.c

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 7cc22736e34c5208c6cf95d22e0336df57f8cddb..5d3976f57522ca111aa657a77003103aee57be0e 100644 (file)
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -20,14 +20,14 @@
 #include "config.h"
 #endif
 
-#include "replacements.h"
+#include <helper/replacements.h>
 
 #include "armv7a.h"
 #include "arm_disassembler.h"
 
 #include "register.h"
-#include "binarybuffer.h"
-#include "command.h"
+#include <helper/binarybuffer.h>
+#include <helper/command.h>
 
 #include <stdlib.h>
 #include <string.h>
@@ -38,17 +38,48 @@ static void armv7a_show_fault_registers(struct target *target)
 {
        uint32_t dfsr, ifsr, dfar, ifar;
        struct armv7a_common *armv7a = target_to_armv7a(target);
-
-       armv7a->read_cp15(target, 0, 0, 5, 0, &dfsr);
-       armv7a->read_cp15(target, 0, 1, 5, 0, &ifsr);
-       armv7a->read_cp15(target, 0, 0, 6, 0, &dfar);
-       armv7a->read_cp15(target, 0, 2, 6, 0, &ifar);
+       struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
+       int retval;
+
+       retval = dpm->prepare(dpm);
+       if (retval != ERROR_OK)
+               return;
+
+       /* ARMV4_5_MRC(cpnum, op1, r0, CRn, CRm, op2) */
+
+       /* c5/c0 - {data, instruction} fault status registers */
+       retval = dpm->instr_read_data_r0(dpm,
+                       ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
+                       &dfsr);
+       if (retval != ERROR_OK)
+               goto done;
+
+       retval = dpm->instr_read_data_r0(dpm,
+                       ARMV4_5_MRC(15, 0, 0, 5, 0, 1),
+                       &ifsr);
+       if (retval != ERROR_OK)
+               goto done;
+
+       /* c6/c0 - {data, instruction} fault address registers */
+       retval = dpm->instr_read_data_r0(dpm,
+                       ARMV4_5_MRC(15, 0, 0, 6, 0, 0),
+                       &dfar);
+       if (retval != ERROR_OK)
+               goto done;
+
+       retval = dpm->instr_read_data_r0(dpm,
+                       ARMV4_5_MRC(15, 0, 0, 6, 0, 2),
+                       &ifar);
+       if (retval != ERROR_OK)
+               goto done;
 
        LOG_USER("Data fault registers        DFSR: %8.8" PRIx32
                        ", DFAR: %8.8" PRIx32, dfsr, dfar);
        LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
                        ", IFAR: %8.8" PRIx32, ifsr, ifar);
 
+done:
+       /* (void) */ dpm->finish(dpm);
 }
 
 int armv7a_arch_state(struct target *target)
@@ -82,6 +113,9 @@ int armv7a_arch_state(struct target *target)
 
        if (armv4_5->core_mode == ARMV4_5_MODE_ABT)
                armv7a_show_fault_registers(target);
+       else if (target->debug_reason == DBG_REASON_WATCHPOINT)
+               LOG_USER("Watchpoint triggered at PC %#08x",
+                               (unsigned) armv7a->dpm.wp_pc);
 
        return ERROR_OK;
 }
@@ -181,7 +215,7 @@ static const struct command_registration armv7a_exec_command_handlers[] = {
        },
        COMMAND_REGISTRATION_DONE
 };
-static const struct command_registration armv7a_command_handlers[] = {
+const struct command_registration armv7a_command_handlers[] = {
        {
                .name = "dap",
                .mode = COMMAND_ANY,
@@ -191,7 +225,3 @@ static const struct command_registration armv7a_command_handlers[] = {
        COMMAND_REGISTRATION_DONE
 };
 
-int armv7a_register_commands(struct command_context *cmd_ctx)
-{
-       return register_commands(cmd_ctx, NULL, armv7a_command_handlers);
-}