ARM: disassemble two more v6+ instructions
[fw/openocd] / src / target / armv7a.c
index 06bc748984c4c8eac129720dcca2fe810af94be7..300ac2835a9867d2dadd736fcee319ce3c7976d0 100644 (file)
 #include "config.h"
 #endif
 
-#include "replacements.h"
+#include <helper/replacements.h>
 
 #include "armv7a.h"
 #include "arm_disassembler.h"
 
 #include "register.h"
-#include "binarybuffer.h"
-#include "command.h"
+#include <helper/binarybuffer.h>
+#include <helper/command.h>
 
 #include <stdlib.h>
 #include <string.h>
@@ -98,22 +98,16 @@ int armv7a_arch_state(struct target *target)
                return ERROR_INVALID_ARGUMENTS;
        }
 
-       LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-                        "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-                        "MMU: %s, D-Cache: %s, I-Cache: %s",
-                armv4_5_state_strings[armv4_5->core_state],
-                Jim_Nvp_value2name_simple(nvp_target_debug_reason,
-                               target->debug_reason)->name,
-                arm_mode_name(armv4_5->core_mode),
-                buf_get_u32(armv4_5->cpsr->value, 0, 32),
-                buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+       armv4_5_arch_state(target);
+
+       LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
                 state[armv7a->armv4_5_mmu.mmu_enabled],
                 state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
                 state[armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 
-       if (armv4_5->core_mode == ARMV4_5_MODE_ABT)
+       if (armv4_5->core_mode == ARM_MODE_ABT)
                armv7a_show_fault_registers(target);
-       else if (target->debug_reason == DBG_REASON_WATCHPOINT)
+       if (target->debug_reason == DBG_REASON_WATCHPOINT)
                LOG_USER("Watchpoint triggered at PC %#08x",
                                (unsigned) armv7a->dpm.wp_pc);