* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
armv7a->armv7a_mmu.ttbr0_mask);
#endif
if (armv7a->armv7a_mmu.ttbr1_used == 1) {
- LOG_INFO("SVC access above %x",
- (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask));
+ LOG_INFO("SVC access above %" PRIx32,
+ (uint32_t)(0xffffffff & armv7a->armv7a_mmu.ttbr0_mask));
armv7a->armv7a_mmu.os_border = 0xffffffff & armv7a->armv7a_mmu.ttbr0_mask;
} else {
/* fix me , default is hard coded LINUX border */
if (*val == va)
LOG_WARNING("virt = phys : MMU disable !!");
if (meminfo) {
- LOG_INFO("%x : %x %s outer shareable %s secured",
+ LOG_INFO("%" PRIx32 " : %" PRIx32 " %s outer shareable %s secured",
va, *val,
NOS == 1 ? "not" : " ",
NS == 1 ? "not" : "");
LOG_INFO("inner: Write-Back, no Write-Allocate");
default:
- LOG_INFO("inner: %x ???", INNER);
+ LOG_INFO("inner: %" PRIx32 " ???", INNER);
}
}
}
command_print(cmd_ctx,
- "D-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes",
+ "D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
armv7a_cache->d_u_size.linelen,
armv7a_cache->d_u_size.associativity,
armv7a_cache->d_u_size.nsets,
armv7a_cache->d_u_size.cachesize);
command_print(cmd_ctx,
- "I-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes",
+ "I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
armv7a_cache->i_size.linelen,
armv7a_cache->i_size.associativity,
armv7a_cache->i_size.nsets,
head = target->head;
while (head != (struct target_list *)NULL) {
curr = head->target;
- if ((curr->state == TARGET_HALTED)) {
- LOG_INFO("Wait flushing data l1 on core %d", curr->coreid);
+ if (curr->state == TARGET_HALTED) {
+ LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid);
retval = _armv7a_flush_all_data(curr);
}
head = head->next;
}
command_print(cmd_ctx,
- "L1 D-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes",
+ "L1 D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
armv7a_cache->d_u_size.linelen,
armv7a_cache->d_u_size.associativity,
armv7a_cache->d_u_size.nsets,
armv7a_cache->d_u_size.cachesize);
command_print(cmd_ctx,
- "L1 I-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes",
+ "L1 I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
armv7a_cache->i_size.linelen,
armv7a_cache->i_size.associativity,
armv7a_cache->i_size.nsets,
armv7a_cache->i_size.cachesize);
- command_print(cmd_ctx, "L2 unified cache Base Address 0x%x, %d ways",
+ command_print(cmd_ctx, "L2 unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
l2x_cache->base, l2x_cache->way);
l2x_cache->base,l2x_cache->way);*/
if (armv7a->armv7a_mmu.armv7a_cache.l2_cache)
LOG_INFO("cache l2 already initialized\n");
- armv7a->armv7a_mmu.armv7a_cache.l2_cache = (void *) l2x_cache;
+ armv7a->armv7a_mmu.armv7a_cache.l2_cache = l2x_cache;
/* initialize l1 / l2x cache function */
armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache
= armv7a_l2x_flush_all_data;
armv7a = target_to_armv7a(curr);
if (armv7a->armv7a_mmu.armv7a_cache.l2_cache)
LOG_ERROR("smp target : cache l2 already initialized\n");
- armv7a->armv7a_mmu.armv7a_cache.l2_cache = (void *) l2x_cache;
+ armv7a->armv7a_mmu.armv7a_cache.l2_cache = l2x_cache;
armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
armv7a_l2x_flush_all_data;
armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
armv7a->multi_processor_system = (mpidr >> 30) & 1;
armv7a->cluster_id = (mpidr >> 8) & 0xf;
armv7a->cpu_id = mpidr & 0x3;
- LOG_INFO("%s cluster %x core %x %s", target->cmd_name,
+ LOG_INFO("%s cluster %x core %x %s", target_name(target),
armv7a->cluster_id,
armv7a->cpu_id,
armv7a->multi_processor_system == 0 ? "multi core" : "mono core");
uint32_t cache_selected, clidr;
uint32_t cache_i_reg, cache_d_reg;
struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache);
- armv7a_read_ttbcr(target);
+ if (!armv7a->is_armv7r)
+ armv7a_read_ttbcr(target);
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
if (retval != ERROR_OK)
goto done;
clidr = (clidr & 0x7000000) >> 23;
- LOG_INFO("number of cache level %d", clidr / 2);
+ LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2));
if ((clidr / 2) > 1) {
/* FIXME not supported present in cortex A8 and later */
/* in cortex A7, A15 */
arm_arch_state(target);
- LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
- state[armv7a->armv7a_mmu.mmu_enabled],
- state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
- state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
+ if (armv7a->is_armv7r) {
+ LOG_USER("D-Cache: %s, I-Cache: %s",
+ state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
+ state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
+ } else {
+ LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
+ state[armv7a->armv7a_mmu.mmu_enabled],
+ state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
+ state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
+ }
if (arm->core_mode == ARM_MODE_ABT)
armv7a_show_fault_registers(target);
{
.name = "cache_config",
.mode = COMMAND_EXEC,
- .help = "cache configuation for a target",
+ .help = "cache configuration for a target",
.usage = "",
.chain = l2_cache_commands,
},