dsp5680xx - flash module clk to freescale cfg value

[fw/openocd] / src / target / armv4_5_mmu.c

diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c
index 861410dd89a3bd28afc224222c5c8a3f35dfe920..5415e83b9fcc3cb16b553282fdb29ac982a73e79 100644 (file)
--- a/src/target/armv4_5_mmu.c
+++ b/src/target/armv4_5_mmu.c
@@ -30,8 +30,11 @@ int armv4_5_mmu_translate_va(struct target *target, struct armv4_5_mmu_common *a
 {
        uint32_t first_lvl_descriptor = 0x0;
        uint32_t second_lvl_descriptor = 0x0;
-       uint32_t ttb = armv4_5_mmu->get_ttb(target);
+       uint32_t ttb;
        int retval;
+       retval = armv4_5_mmu->get_ttb(target, &ttb);
+       if (retval != ERROR_OK)
+         return retval;
 
        retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
                (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
@@ -128,19 +131,25 @@ int armv4_5_mmu_read_physical(struct target *target, struct armv4_5_mmu_common *
                return ERROR_TARGET_NOT_HALTED;
 
        /* disable MMU and data (or unified) cache */
-       armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+       retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+       if (retval !=ERROR_OK)
+               return retval;
 
        retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
+       if (retval !=ERROR_OK)
+               return retval;
 
        /* reenable MMU / cache */
-       armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
+       retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
                armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
                armv4_5_mmu->armv4_5_cache.i_cache_enabled);
+       if (retval !=ERROR_OK)
+               return retval;
 
        return retval;
 }
 
-int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
 {
        int retval;
 
@@ -148,14 +157,20 @@ int armv4_5_mmu_write_physical(struct target *target, struct armv4_5_mmu_common
                return ERROR_TARGET_NOT_HALTED;
 
        /* disable MMU and data (or unified) cache */
-       armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+       retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
+       if (retval !=ERROR_OK)
+               return retval;
 
        retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
+       if (retval !=ERROR_OK)
+               return retval;
 
        /* reenable MMU / cache */
-       armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
+       retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
                armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
                armv4_5_mmu->armv4_5_cache.i_cache_enabled);
+       if (retval !=ERROR_OK)
+               return retval;
 
        return retval;
 }