kinetis: Revise CPU un-securing code

[fw/openocd] / src / target / armv4_5_cache.h

diff --git a/src/target/armv4_5_cache.h b/src/target/armv4_5_cache.h
index 71e3203c08617b6d2b3e1e19c92557734180f9a9..a1777e802bf1a9ccab7cb899f2c3083b759db0e5 100644 (file)
--- a/src/target/armv4_5_cache.h
+++ b/src/target/armv4_5_cache.h
@@ -15,43 +15,39 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
+
 #ifndef ARMV4_5_CACHE_H
 #define ARMV4_5_CACHE_H
 
-#include "types.h"
-
-struct command_context_s;
+struct command_context;
 
-typedef struct armv4_5_cachesize_s
-{
+struct armv4_5_cachesize {
        int linelen;
        int associativity;
        int nsets;
        int cachesize;
-} armv4_5_cachesize_t;
+};
 
-typedef struct armv4_5_cache_common_s
-{
+struct armv4_5_cache_common {
        int ctype;      /* specify supported cache operations */
        int separate;   /* separate caches or unified cache */
-       armv4_5_cachesize_t d_u_size;   /* data cache */
-       armv4_5_cachesize_t i_size; /* instruction cache */
+       struct armv4_5_cachesize d_u_size;      /* data cache */
+       struct armv4_5_cachesize i_size; /* instruction cache */
        int i_cache_enabled;
        int d_u_cache_enabled;
-} armv4_5_cache_common_t;
+};
 
 int armv4_5_identify_cache(uint32_t cache_type_reg,
-               armv4_5_cache_common_t *cache);
+               struct armv4_5_cache_common *cache);
 int armv4_5_cache_state(uint32_t cp15_control_reg,
-               armv4_5_cache_common_t *cache);
+               struct armv4_5_cache_common *cache);
 
-int armv4_5_handle_cache_info_command(struct command_context_s *cmd_ctx,
-               armv4_5_cache_common_t *armv4_5_cache);
+int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx,
+               struct armv4_5_cache_common *armv4_5_cache);
 
-enum
-{
+enum {
        ARMV4_5_D_U_CACHE_ENABLED = 0x4,
        ARMV4_5_I_CACHE_ENABLED = 0x1000,
        ARMV4_5_WRITE_BUFFER_ENABLED = 0x8,