ARM11 command handling fixes

[fw/openocd] / src / target / armv4_5_cache.h

diff --git a/src/target/armv4_5_cache.h b/src/target/armv4_5_cache.h
index 766718b6a7f9409b7868563fd78601a65aba9e09..44bc212e0ab9a00d4ff1b64a48c30d29c624bce9 100644 (file)
--- a/src/target/armv4_5_cache.h
+++ b/src/target/armv4_5_cache.h
@@ -21,7 +21,8 @@
 #define ARMV4_5_CACHE_H
 
 #include "types.h"
-#include "command.h"
+
+struct command_context_s;
 
 typedef struct armv4_5_cachesize_s
 {
@@ -41,9 +42,17 @@ typedef struct armv4_5_cache_common_s
        int d_u_cache_enabled;
 } armv4_5_cache_common_t;
 
-extern int armv4_5_identify_cache(u32 cache_type_reg, armv4_5_cache_common_t *cache);
-extern int armv4_5_cache_state(u32 cp15_control_reg, armv4_5_cache_common_t *cache);
+extern int armv4_5_identify_cache(uint32_t cache_type_reg, armv4_5_cache_common_t *cache);
+extern int armv4_5_cache_state(uint32_t cp15_control_reg, armv4_5_cache_common_t *cache);
 
 extern int armv4_5_handle_cache_info_command(struct command_context_s *cmd_ctx, armv4_5_cache_common_t *armv4_5_cache);
 
+enum
+{
+       ARMV4_5_D_U_CACHE_ENABLED = 0x4,
+       ARMV4_5_I_CACHE_ENABLED = 0x1000,
+       ARMV4_5_WRITE_BUFFER_ENABLED = 0x8,
+       ARMV4_5_CACHE_RR_BIT = 0x5000,
+};
+
 #endif /* ARMV4_5_CACHE_H */