dsp5680xx - mark erase after unlocking flash

[fw/openocd] / src / target / armv4_5_cache.c

diff --git a/src/target/armv4_5_cache.c b/src/target/armv4_5_cache.c
index 326f10ee8234b68b4c15962bf2dbc3792322249d..dcbcef3a131947d2ca0941b61244f0d96aac1c45 100644 (file)
--- a/src/target/armv4_5_cache.c
+++ b/src/target/armv4_5_cache.c
@@ -17,12 +17,14 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
-#include "armv4_5_cache.h"
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
 
-#include "log.h"
-#include "command.h"
+#include "armv4_5_cache.h"
+#include <helper/log.h>
 
-int armv4_5_identify_cache(u32 cache_type_reg, armv4_5_cache_common_t *cache)
+int armv4_5_identify_cache(uint32_t cache_type_reg, struct armv4_5_cache_common *cache)
 {
        int size, assoc, M, len, multiplier;
 
@@ -59,7 +61,7 @@ int armv4_5_identify_cache(u32 cache_type_reg, armv4_5_cache_common_t *cache)
                M = (cache_type_reg & 0x4) >> 2;
                len = (cache_type_reg & 0x3);
                multiplier = 2 + M;
-               
+
                if ((assoc != 0) || (M != 1)) /* assoc 0 and M 1 means cache absent */
                {
                        /* cache is present */
@@ -81,32 +83,32 @@ int armv4_5_identify_cache(u32 cache_type_reg, armv4_5_cache_common_t *cache)
        {
                cache->i_size = cache->d_u_size;
        }
-       
+
        return ERROR_OK;
 }
 
-int armv4_5_handle_cache_info_command(struct command_context_s *cmd_ctx, armv4_5_cache_common_t *armv4_5_cache)
+int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx, struct armv4_5_cache_common *armv4_5_cache)
 {
        if (armv4_5_cache->ctype == -1)
        {
                command_print(cmd_ctx, "cache not yet identified");
                return ERROR_OK;
        }
-               
-       command_print(cmd_ctx, "cache type: 0x%1.1x, %s", armv4_5_cache->ctype, 
+
+       command_print(cmd_ctx, "cache type: 0x%1.1x, %s", armv4_5_cache->ctype,
                (armv4_5_cache->separate) ? "separate caches" : "unified cache");
 
-       command_print(cmd_ctx, "D-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x", 
+       command_print(cmd_ctx, "D-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
                armv4_5_cache->d_u_size.linelen,
                armv4_5_cache->d_u_size.associativity,
                armv4_5_cache->d_u_size.nsets,
                armv4_5_cache->d_u_size.cachesize);
 
-       command_print(cmd_ctx, "I-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x", 
+       command_print(cmd_ctx, "I-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
                armv4_5_cache->i_size.linelen,
                armv4_5_cache->i_size.associativity,
                armv4_5_cache->i_size.nsets,
                armv4_5_cache->i_size.cachesize);
-       
+
        return ERROR_OK;
 }