* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * Copyright (C) 2009 by Øyvind Harboe *
+ * oyvind.harboe@zylin.com *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
#include "register.h"
#include "target.h"
+#include "log.h"
+#include "etm.h"
-enum armv4_5_mode
+typedef enum armv4_5_mode
{
- ARMV4_5_MODE_USR = 16,
- ARMV4_5_MODE_FIQ = 17,
- ARMV4_5_MODE_IRQ = 18,
- ARMV4_5_MODE_SVC = 19,
+ ARMV4_5_MODE_USR = 16,
+ ARMV4_5_MODE_FIQ = 17,
+ ARMV4_5_MODE_IRQ = 18,
+ ARMV4_5_MODE_SVC = 19,
ARMV4_5_MODE_ABT = 23,
ARMV4_5_MODE_UND = 27,
ARMV4_5_MODE_SYS = 31,
ARMV4_5_MODE_ANY = -1
-};
+} armv4_5_mode_t;
-extern char* armv4_5_mode_strings[];
+extern char** armv4_5_mode_strings;
-enum armv4_5_state
+typedef enum armv4_5_state
{
ARMV4_5_STATE_ARM,
ARMV4_5_STATE_THUMB,
ARMV4_5_STATE_JAZELLE,
-};
+} armv4_5_state_t;
extern char* armv4_5_state_strings[];
cache->reg_list[armv4_5_core_reg_map[mode][num]]
/* offsets into armv4_5 core register cache */
-enum
+enum
{
ARMV4_5_CPSR = 31,
ARMV4_5_SPSR_FIQ = 32,
#define ARMV4_5_COMMON_MAGIC 0x0A450A45
-typedef struct armv4_5_common_s
+/* NOTE: this is being morphed into a generic toplevel holder for ARMs. */
+#define armv4_5_common_s arm
+
+/**
+ * Represents a generic ARM core, with standard application registers.
+ *
+ * There are sixteen application registers (including PC, SP, LR) and a PSR.
+ * Cortex-M series cores do not support as many core states or shadowed
+ * registers as traditional ARM cores, and only support Thumb2 instructions.
+ */
+struct arm
{
int common_magic;
- reg_cache_t *core_cache;
- enum armv4_5_mode core_mode;
+ struct reg_cache *core_cache;
+
+ int /* armv4_5_mode */ core_mode;
enum armv4_5_state core_state;
+
+ /** Flag reporting unavailability of the BKPT instruction. */
+ bool is_armv4;
+
+ /** Handle for the Embedded Trace Module, if one is present. */
+ struct etm_context *etm;
+
int (*full_context)(struct target_s *target);
- int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);
- int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, u32 value);
+ int (*read_core_reg)(struct target_s *target,
+ int num, enum armv4_5_mode mode);
+ int (*write_core_reg)(struct target_s *target,
+ int num, enum armv4_5_mode mode, uint32_t value);
void *arch_info;
-} armv4_5_common_t;
+};
+
+#define target_to_armv4_5 target_to_arm
+
+/** Convert target handle to generic ARM target state handle. */
+static inline struct arm *target_to_arm(struct target_s *target)
+{
+ return target->arch_info;
+}
+
+static inline bool is_arm(struct arm *arm)
+{
+ return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
+}
-typedef struct armv4_5_algorithm_s
+struct armv4_5_algorithm
{
int common_magic;
-
+
enum armv4_5_mode core_mode;
enum armv4_5_state core_state;
-} armv4_5_algorithm_t;
+};
-typedef struct armv4_5_core_reg_s
+struct armv4_5_core_reg
{
int num;
enum armv4_5_mode mode;
target_t *target;
- armv4_5_common_t *armv4_5_common;
-} armv4_5_core_reg_t;
+ struct arm *armv4_5_common;
+};
-extern reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common);
-extern enum armv4_5_mode armv4_5_number_to_mode(int number);
-extern int armv4_5_mode_to_number(enum armv4_5_mode mode);
+struct reg_cache* armv4_5_build_reg_cache(target_t *target,
+ struct arm *armv4_5_common);
-extern int armv4_5_arch_state(struct target_s *target, char *buf, int buf_size);
-extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
-extern int armv4_5_invalidate_core_regs(target_t *target);
+/* map psr mode bits to linear number */
+static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
+{
+ switch (mode)
+ {
+ case ARMV4_5_MODE_USR: return 0; break;
+ case ARMV4_5_MODE_FIQ: return 1; break;
+ case ARMV4_5_MODE_IRQ: return 2; break;
+ case ARMV4_5_MODE_SVC: return 3; break;
+ case ARMV4_5_MODE_ABT: return 4; break;
+ case ARMV4_5_MODE_UND: return 5; break;
+ case ARMV4_5_MODE_SYS: return 6; break;
+ case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
+ default:
+ LOG_ERROR("invalid mode value encountered %d", mode);
+ return -1;
+ }
+}
+
+/* map linear number to mode bits */
+static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
+{
+ switch (number)
+ {
+ case 0: return ARMV4_5_MODE_USR; break;
+ case 1: return ARMV4_5_MODE_FIQ; break;
+ case 2: return ARMV4_5_MODE_IRQ; break;
+ case 3: return ARMV4_5_MODE_SVC; break;
+ case 4: return ARMV4_5_MODE_ABT; break;
+ case 5: return ARMV4_5_MODE_UND; break;
+ case 6: return ARMV4_5_MODE_SYS; break;
+ default:
+ LOG_ERROR("mode index out of bounds %d", number);
+ return ARMV4_5_MODE_ANY;
+ }
+};
+
+int armv4_5_arch_state(struct target_s *target);
+int armv4_5_get_gdb_reg_list(target_t *target,
+ reg_t **reg_list[], int *reg_list_size);
-extern int armv4_5_register_commands(struct command_context_s *cmd_ctx);
-extern int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
+int armv4_5_register_commands(struct command_context_s *cmd_ctx);
+int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5);
-extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
+int armv4_5_run_algorithm(struct target_s *target,
+ int num_mem_params, struct mem_param *mem_params,
+ int num_reg_params, struct reg_param *reg_params,
+ uint32_t entry_point, uint32_t exit_point,
+ int timeout_ms, void *arch_info);
-extern int armv4_5_invalidate_core_regs(target_t *target);
+int armv4_5_invalidate_core_regs(target_t *target);
/* ARM mode instructions
*/
-
+
/* Store multiple increment after
* Rn: base register
* List: for each bit in list: store register
* S: in priviledged mode: store user-mode registers
- * W=1: update the base register. W=0: leave the base register untouched
+ * W = 1: update the base register. W = 0: leave the base register untouched
*/
#define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
* Rn: base register
* List: for each bit in list: store register
* S: in priviledged mode: store user-mode registers
- * W=1: update the base register. W=0: leave the base register untouched
+ * W = 1: update the base register. W = 0: leave the base register untouched
*/
#define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
#define ARMV4_5_NOP (0xe1a08008)
/* Move PSR to general purpose register
- * R=1: SPSR R=0: CPSR
+ * R = 1: SPSR R = 0: CPSR
* Rn: target register
*/
#define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
#define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
/* Move general purpose register to PSR
- * R=1: SPSR R=0: CPSR
+ * R = 1: SPSR R = 0: CPSR
* Field: Field mask
* 1: control field 2: extension field 4: status field 8: flags field
* Rm: source register
* CRm: second coprocessor operand
* op2: Second coprocessor opcode
*/
-#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
+#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
/* Move to coprocessor from ARM register
* CP: Coprocessor number
* CRm: second coprocessor operand
* op2: Second coprocessor opcode
*/
-#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
+#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
/* Breakpoint instruction (ARMv5)
* Im: 16-bit immediate
/* Thumb mode instructions
*/
-
+
/* Store register (Thumb mode)
* Rd: source register
* Rn: base register
* List: for each bit in list: store register
*/
#define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
-
+
/* Load register with PC relative addressing
* Rd: register to load
*/
-#define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
-
+#define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
+
/* Move hi register (Thumb mode)
* Rd: destination register
* Rm: source register
*/
#define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
+/* build basic mrc/mcr opcode */
+
+static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
+{
+ uint32_t t = 0;
+ t|=op1<<21;
+ t|=op2<<5;
+ t|=CRn<<16;
+ t|=CRm<<0;
+ return t;
+}
+
+
+
+
#endif /* ARMV4_5_H */
projects / fw / openocd / blobdiff