- Fixes '=' whitespace

[fw/openocd] / src / target / armv4_5.h

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index b4ac07378b621238679712bcb145b2c05e9238aa..8e9710a87633a9d83e78a32f7bad090e7c133aab 100644 (file)
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -29,10 +29,10 @@
 
 typedef enum armv4_5_mode
 {
-       ARMV4_5_MODE_USR = 16, 
-       ARMV4_5_MODE_FIQ = 17, 
-       ARMV4_5_MODE_IRQ = 18, 
-       ARMV4_5_MODE_SVC = 19, 
+       ARMV4_5_MODE_USR = 16,
+       ARMV4_5_MODE_FIQ = 17,
+       ARMV4_5_MODE_IRQ = 18,
+       ARMV4_5_MODE_SVC = 19,
        ARMV4_5_MODE_ABT = 23,
        ARMV4_5_MODE_UND = 27,
        ARMV4_5_MODE_SYS = 31,
@@ -58,7 +58,7 @@ extern int armv4_5_core_reg_map[7][17];
                cache->reg_list[armv4_5_core_reg_map[mode][num]]
 
 /* offsets into armv4_5 core register cache */
-enum 
+enum
 {
        ARMV4_5_CPSR = 31,
        ARMV4_5_SPSR_FIQ = 32,
@@ -78,14 +78,14 @@ typedef struct armv4_5_common_s
        enum armv4_5_state core_state;
        int (*full_context)(struct target_s *target);
        int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);
-       int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, u32 value);
+       int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value);
        void *arch_info;
 } armv4_5_common_t;
 
 typedef struct armv4_5_algorithm_s
 {
        int common_magic;
-               
+
        enum armv4_5_mode core_mode;
        enum armv4_5_state core_state;
 } armv4_5_algorithm_t;
@@ -113,7 +113,7 @@ static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
                case ARMV4_5_MODE_UND: return 5; break;
                case ARMV4_5_MODE_SYS: return 6; break;
                case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
-               default: 
+               default:
                        LOG_ERROR("invalid mode value encountered");
                        return -1;
        }
@@ -122,7 +122,7 @@ static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
 /* map linear number to mode bits */
 static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
 {
-       switch(number)
+       switch (number)
        {
                case 0: return ARMV4_5_MODE_USR; break;
                case 1: return ARMV4_5_MODE_FIQ; break;
@@ -131,32 +131,30 @@ static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
                case 4: return ARMV4_5_MODE_ABT; break;
                case 5: return ARMV4_5_MODE_UND; break;
                case 6: return ARMV4_5_MODE_SYS; break;
-               default: 
+               default:
                        LOG_ERROR("mode index out of bounds");
-                       return -1;
+                       return ARMV4_5_MODE_ANY;
        }
 };
 
-
 extern int armv4_5_arch_state(struct target_s *target);
 extern int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
-extern int armv4_5_invalidate_core_regs(target_t *target);
 
 extern int armv4_5_register_commands(struct command_context_s *cmd_ctx);
 extern int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
 
-extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
+extern int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info);
 
 extern int armv4_5_invalidate_core_regs(target_t *target);
 
 /* ARM mode instructions
  */
- 
+
 /* Store multiple increment after
  * Rn: base register
  * List: for each bit in list: store register
  * S: in priviledged mode: store user-mode registers
- * W=1: update the base register. W=0: leave the base register untouched
+ * W = 1: update the base register. W = 0: leave the base register untouched
  */
 #define ARMV4_5_STMIA(Rn, List, S, W)  (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 
@@ -164,7 +162,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * Rn: base register
  * List: for each bit in list: store register
  * S: in priviledged mode: store user-mode registers
- * W=1: update the base register. W=0: leave the base register untouched
+ * W = 1: update the base register. W = 0: leave the base register untouched
  */
 #define ARMV4_5_LDMIA(Rn, List, S, W)  (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 
@@ -172,7 +170,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
 #define ARMV4_5_NOP                                    (0xe1a08008)
 
 /* Move PSR to general purpose register
- * R=1: SPSR R=0: CPSR
+ * R = 1: SPSR R = 0: CPSR
  * Rn: target register
  */
 #define ARMV4_5_MRS(Rn, R)                     (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
@@ -190,7 +188,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
 #define ARMV4_5_LDR(Rd, Rn)                    (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 
 /* Move general purpose register to PSR
- * R=1: SPSR R=0: CPSR
+ * R = 1: SPSR R = 0: CPSR
  * Field: Field mask
  * 1: control field 2: extension field 4: status field 8: flags field
  * Rm: source register
@@ -241,7 +239,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * CRm: second coprocessor operand
  * op2: Second coprocessor opcode
  */
-#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) 
+#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 
 /* Move to coprocessor from ARM register
  * CP: Coprocessor number
@@ -251,7 +249,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * CRm: second coprocessor operand
  * op2: Second coprocessor opcode
  */
-#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21)) 
+#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 
 /* Breakpoint instruction (ARMv5)
  * Im: 16-bit immediate
@@ -261,7 +259,7 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
 
 /* Thumb mode instructions
  */
- 
+
 /* Store register (Thumb mode)
  * Rd: source register
  * Rn: base register
@@ -279,12 +277,12 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
  * List: for each bit in list: store register
  */
 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
- 
+
 /* Load register with PC relative addressing
  * Rd: register to load
  */
-#define ARMV4_5_T_LDR_PCREL(Rd)        ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16)) 
- 
+#define ARMV4_5_T_LDR_PCREL(Rd)        ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
+
 /* Move hi register (Thumb mode)
  * Rd: destination register
  * Rm: source register