XScale: add stub {read,write}_phys routines

[fw/openocd] / src / target / armv4_5.h

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 5fef0942ccd37cb618b6e73c4b5f169a7ba74f03..822d14393b2eb94c00ca7573fe907fab8bd9e88d 100644 (file)
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -27,6 +27,8 @@
 #define ARMV4_5_H
 
 #include "target.h"
+#include "command.h"
+
 
 typedef enum armv4_5_mode
 {
@@ -35,48 +37,38 @@ typedef enum armv4_5_mode
        ARMV4_5_MODE_IRQ = 18,
        ARMV4_5_MODE_SVC = 19,
        ARMV4_5_MODE_ABT = 23,
+       ARM_MODE_MON = 26,
        ARMV4_5_MODE_UND = 27,
        ARMV4_5_MODE_SYS = 31,
        ARMV4_5_MODE_ANY = -1
 } armv4_5_mode_t;
 
+const char *arm_mode_name(unsigned psr_mode);
+bool is_arm_mode(unsigned psr_mode);
+
 int armv4_5_mode_to_number(enum armv4_5_mode mode);
 enum armv4_5_mode armv4_5_number_to_mode(int number);
 
-extern const char **armv4_5_mode_strings;
-
 typedef enum armv4_5_state
 {
        ARMV4_5_STATE_ARM,
        ARMV4_5_STATE_THUMB,
        ARMV4_5_STATE_JAZELLE,
+       ARM_STATE_THUMB_EE,
 } armv4_5_state_t;
 
 extern char* armv4_5_state_strings[];
 
-extern int armv4_5_core_reg_map[7][17];
+extern const int armv4_5_core_reg_map[8][17];
 
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
                cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
-#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
-               cache->reg_list[armv4_5_core_reg_map[mode][num]]
 
-/* offsets into armv4_5 core register cache */
-enum
-{
-       ARMV4_5_CPSR = 31,
-       ARMV4_5_SPSR_FIQ = 32,
-       ARMV4_5_SPSR_IRQ = 33,
-       ARMV4_5_SPSR_SVC = 34,
-       ARMV4_5_SPSR_ABT = 35,
-       ARMV4_5_SPSR_UND = 36
-};
+/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
+enum { ARMV4_5_CPSR = 31, };
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
 
-/* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
-#define armv4_5_common_s arm
-
 /**
  * Represents a generic ARM core, with standard application registers.
  *
@@ -89,19 +81,41 @@ struct arm
        int common_magic;
        struct reg_cache *core_cache;
 
-       int /* armv4_5_mode */ core_mode;
+       /** Handle to the CPSR; valid in all core modes. */
+       struct reg *cpsr;
+
+       /** Handle to the SPSR; valid only in core modes with an SPSR. */
+       struct reg *spsr;
+
+       const int *map;
+
+       /**
+        * Indicates what registers are in the ARM state core register set.
+        * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
+        * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
+        * more registers are shadowed, for "Secure Monitor" mode.
+        */
+       enum armv4_5_mode core_type;
+
+       enum armv4_5_mode core_mode;
        enum armv4_5_state core_state;
 
        /** Flag reporting unavailability of the BKPT instruction. */
        bool is_armv4;
 
+       /** Backpointer to the target. */
+       struct target *target;
+
+       /** Handle for the debug module, if one is present. */
+       struct arm_dpm *dpm;
+
        /** Handle for the Embedded Trace Module, if one is present. */
        struct etm_context *etm;
 
        int (*full_context)(struct target *target);
-       int (*read_core_reg)(struct target *target,
+       int (*read_core_reg)(struct target *target, struct reg *reg,
                        int num, enum armv4_5_mode mode);
-       int (*write_core_reg)(struct target *target,
+       int (*write_core_reg)(struct target *target, struct reg *reg,
                        int num, enum armv4_5_mode mode, uint32_t value);
        void *arch_info;
 };
@@ -127,12 +141,13 @@ struct armv4_5_algorithm
        enum armv4_5_state core_state;
 };
 
-struct armv4_5_core_reg
+struct arm_reg
 {
        int num;
        enum armv4_5_mode mode;
        struct target *target;
        struct arm *armv4_5_common;
+       uint32_t value;
 };
 
 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
@@ -142,7 +157,8 @@ int armv4_5_arch_state(struct target *target);
 int armv4_5_get_gdb_reg_list(struct target *target,
                struct reg **reg_list[], int *reg_list_size);
 
-int armv4_5_register_commands(struct command_context *cmd_ctx);
+extern const struct command_registration arm_command_handlers[];
+
 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 
 int armv4_5_run_algorithm(struct target *target,
@@ -151,13 +167,16 @@ int armv4_5_run_algorithm(struct target *target,
                uint32_t entry_point, uint32_t exit_point,
                int timeout_ms, void *arch_info);
 
-int armv4_5_invalidate_core_regs(struct target *target);
-
 int arm_checksum_memory(struct target *target,
                uint32_t address, uint32_t count, uint32_t *checksum);
 int arm_blank_check_memory(struct target *target,
                uint32_t address, uint32_t count, uint32_t *blank);
 
+void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
+struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
+
+extern struct reg arm_gdb_dummy_fp_reg;
+extern struct reg arm_gdb_dummy_fps_reg;
 
 /* ARM mode instructions
  */