fileio: improve API types

[fw/openocd] / src / target / armv4_5.h

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 3c65069e024dde1e3ba25998065884ac3483f71f..5fef0942ccd37cb618b6e73c4b5f169a7ba74f03 100644 (file)
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -26,10 +26,7 @@
 #ifndef ARMV4_5_H
 #define ARMV4_5_H
 
-#include "register.h"
 #include "target.h"
-#include "log.h"
-#include "etm.h"
 
 typedef enum armv4_5_mode
 {
@@ -43,7 +40,10 @@ typedef enum armv4_5_mode
        ARMV4_5_MODE_ANY = -1
 } armv4_5_mode_t;
 
-extern char** armv4_5_mode_strings;
+int armv4_5_mode_to_number(enum armv4_5_mode mode);
+enum armv4_5_mode armv4_5_number_to_mode(int number);
+
+extern const char **armv4_5_mode_strings;
 
 typedef enum armv4_5_state
 {
@@ -84,7 +84,7 @@ enum
  * Cortex-M series cores do not support as many core states or shadowed
  * registers as traditional ARM cores, and only support Thumb2 instructions.
  */
-typedef struct arm
+struct arm
 {
        int common_magic;
        struct reg_cache *core_cache;
@@ -98,18 +98,18 @@ typedef struct arm
        /** Handle for the Embedded Trace Module, if one is present. */
        struct etm_context *etm;
 
-       int (*full_context)(struct target_s *target);
-       int (*read_core_reg)(struct target_s *target,
+       int (*full_context)(struct target *target);
+       int (*read_core_reg)(struct target *target,
                        int num, enum armv4_5_mode mode);
-       int (*write_core_reg)(struct target_s *target,
+       int (*write_core_reg)(struct target *target,
                        int num, enum armv4_5_mode mode, uint32_t value);
        void *arch_info;
-} armv4_5_common_t;
+};
 
 #define target_to_armv4_5 target_to_arm
 
 /** Convert target handle to generic ARM target state handle. */
-static inline struct arm *target_to_arm(struct target_s *target)
+static inline struct arm *target_to_arm(struct target *target)
 {
        return target->arch_info;
 }
@@ -131,64 +131,33 @@ struct armv4_5_core_reg
 {
        int num;
        enum armv4_5_mode mode;
-       target_t *target;
-       armv4_5_common_t *armv4_5_common;
+       struct target *target;
+       struct arm *armv4_5_common;
 };
 
-struct reg_cache* armv4_5_build_reg_cache(target_t *target,
-               armv4_5_common_t *armv4_5_common);
+struct reg_cache* armv4_5_build_reg_cache(struct target *target,
+               struct arm *armv4_5_common);
 
-/* map psr mode bits to linear number */
-static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
-{
-       switch (mode)
-       {
-               case ARMV4_5_MODE_USR: return 0; break;
-               case ARMV4_5_MODE_FIQ: return 1; break;
-               case ARMV4_5_MODE_IRQ: return 2; break;
-               case ARMV4_5_MODE_SVC: return 3; break;
-               case ARMV4_5_MODE_ABT: return 4; break;
-               case ARMV4_5_MODE_UND: return 5; break;
-               case ARMV4_5_MODE_SYS: return 6; break;
-               case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
-               default:
-                       LOG_ERROR("invalid mode value encountered %d", mode);
-                       return -1;
-       }
-}
-
-/* map linear number to mode bits */
-static __inline enum armv4_5_mode armv4_5_number_to_mode(int number)
-{
-       switch (number)
-       {
-               case 0: return ARMV4_5_MODE_USR; break;
-               case 1: return ARMV4_5_MODE_FIQ; break;
-               case 2: return ARMV4_5_MODE_IRQ; break;
-               case 3: return ARMV4_5_MODE_SVC; break;
-               case 4: return ARMV4_5_MODE_ABT; break;
-               case 5: return ARMV4_5_MODE_UND; break;
-               case 6: return ARMV4_5_MODE_SYS; break;
-               default:
-                       LOG_ERROR("mode index out of bounds %d", number);
-                       return ARMV4_5_MODE_ANY;
-       }
-};
+int armv4_5_arch_state(struct target *target);
+int armv4_5_get_gdb_reg_list(struct target *target,
+               struct reg **reg_list[], int *reg_list_size);
 
-int armv4_5_arch_state(struct target_s *target);
-int armv4_5_get_gdb_reg_list(target_t *target,
-               reg_t **reg_list[], int *reg_list_size);
+int armv4_5_register_commands(struct command_context *cmd_ctx);
+int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 
-int armv4_5_register_commands(struct command_context_s *cmd_ctx);
-int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
-
-int armv4_5_run_algorithm(struct target_s *target,
+int armv4_5_run_algorithm(struct target *target,
                int num_mem_params, struct mem_param *mem_params,
                int num_reg_params, struct reg_param *reg_params,
                uint32_t entry_point, uint32_t exit_point,
                int timeout_ms, void *arch_info);
 
-int armv4_5_invalidate_core_regs(target_t *target);
+int armv4_5_invalidate_core_regs(struct target *target);
+
+int arm_checksum_memory(struct target *target,
+               uint32_t address, uint32_t count, uint32_t *checksum);
+int arm_blank_check_memory(struct target *target,
+               uint32_t address, uint32_t count, uint32_t *blank);
+
 
 /* ARM mode instructions
  */
@@ -369,7 +338,4 @@ static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_
        return t;
 }
 
-
-
-
 #endif /* ARMV4_5_H */