mips: fix gaffe when removing dynamic array allocation

[fw/openocd] / src / target / armv4_5.h

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index c8fc558082fe502e7cdaefc7683786284d66878a..49314554ddc8f5d75a2b66e154eb0975335bf885 100644 (file)
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -62,23 +62,11 @@ extern const int armv4_5_core_reg_map[8][17];
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
                cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
 
-/* offsets into armv4_5 core register cache */
-enum
-{
-       ARMV4_5_CPSR = 31,
-       ARMV4_5_SPSR_FIQ = 32,
-       ARMV4_5_SPSR_IRQ = 33,
-       ARMV4_5_SPSR_SVC = 34,
-       ARMV4_5_SPSR_ABT = 35,
-       ARMV4_5_SPSR_UND = 36,
-       ARM_SPSR_MON = 39,
-};
+/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
+enum { ARMV4_5_CPSR = 31, };
 
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
 
-/* NOTE:  this is being morphed into a generic toplevel holder for ARMs. */
-#define armv4_5_common_s arm
-
 /**
  * Represents a generic ARM core, with standard application registers.
  *
@@ -91,6 +79,14 @@ struct arm
        int common_magic;
        struct reg_cache *core_cache;
 
+       /** Handle to the CPSR; valid in all core modes. */
+       struct reg *cpsr;
+
+       /** Handle to the SPSR; valid only in core modes with an SPSR. */
+       struct reg *spsr;
+
+       const int *map;
+
        /**
         * Indicates what registers are in the ARM state core register set.
         * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
@@ -167,6 +163,9 @@ int arm_checksum_memory(struct target *target,
 int arm_blank_check_memory(struct target *target,
                uint32_t address, uint32_t count, uint32_t *blank);
 
+void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
+struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
+
 extern struct reg arm_gdb_dummy_fp_reg;
 extern struct reg arm_gdb_dummy_fps_reg;