ARM: rename armv4_5_algorithm as arm_algorithm

[fw/openocd] / src / target / armv4_5.h

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 7229a6c0bdbeba1080a9cc3cd29eee3b49c80737..0b28301332673c147f707dcd816400357a74c2eb 100644 (file)
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -26,48 +26,56 @@
 #ifndef ARMV4_5_H
 #define ARMV4_5_H
 
-#include "target.h"
-#include "command.h"
+#include <target/target.h>
+#include <helper/command.h>
 
 
-typedef enum armv4_5_mode
-{
-       ARMV4_5_MODE_USR = 16,
-       ARMV4_5_MODE_FIQ = 17,
-       ARMV4_5_MODE_IRQ = 18,
-       ARMV4_5_MODE_SVC = 19,
-       ARMV4_5_MODE_ABT = 23,
+/* These numbers match the five low bits of the *PSR registers on
+ * "classic ARM" processors, which build on the ARMv4 processor
+ * modes and register set.
+ */
+enum arm_mode {
+       ARM_MODE_USR = 16,
+       ARM_MODE_FIQ = 17,
+       ARM_MODE_IRQ = 18,
+       ARM_MODE_SVC = 19,
+       ARM_MODE_ABT = 23,
        ARM_MODE_MON = 26,
-       ARMV4_5_MODE_UND = 27,
-       ARMV4_5_MODE_SYS = 31,
-       ARMV4_5_MODE_ANY = -1
-} armv4_5_mode_t;
+       ARM_MODE_UND = 27,
+       ARM_MODE_SYS = 31,
+       ARM_MODE_ANY = -1
+};
 
 const char *arm_mode_name(unsigned psr_mode);
 bool is_arm_mode(unsigned psr_mode);
 
-int armv4_5_mode_to_number(enum armv4_5_mode mode);
-enum armv4_5_mode armv4_5_number_to_mode(int number);
-
-typedef enum armv4_5_state
-{
-       ARMV4_5_STATE_ARM,
-       ARMV4_5_STATE_THUMB,
-       ARMV4_5_STATE_JAZELLE,
+/* The PSR "T" and "J" bits define the mode of "classic ARM" cores */
+enum arm_state {
+       ARM_STATE_ARM,
+       ARM_STATE_THUMB,
+       ARM_STATE_JAZELLE,
        ARM_STATE_THUMB_EE,
-} armv4_5_state_t;
+};
 
-extern char* armv4_5_state_strings[];
+extern const char *arm_state_strings[];
+
+/* OBSOLETE, DO NOT USE IN NEW CODE!  The "number" of an arm_mode is an
+ * index into the armv4_5_core_reg_map array.  Its remaining users are
+ * remnants which could as easily walk * the register cache directly as
+ * use the expensive ARMV4_5_CORE_REG_MODE() macro.
+ */
+int arm_mode_to_number(enum arm_mode mode);
+enum arm_mode armv4_5_number_to_mode(int number);
 
 extern const int armv4_5_core_reg_map[8][17];
 
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
-               cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
+               cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]
 
 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
 enum { ARMV4_5_CPSR = 31, };
 
-#define ARMV4_5_COMMON_MAGIC 0x0A450A45
+#define ARM_COMMON_MAGIC 0x0A450A45
 
 /**
  * Represents a generic ARM core, with standard application registers.
@@ -91,18 +99,24 @@ struct arm
 
        /**
         * Indicates what registers are in the ARM state core register set.
-        * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
+        * ARM_MODE_ANY indicates the standard set of 37 registers,
         * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
         * more registers are shadowed, for "Secure Monitor" mode.
         */
-       enum armv4_5_mode core_type;
+       enum arm_mode core_type;
 
-       enum armv4_5_mode core_mode;
-       enum armv4_5_state core_state;
+       enum arm_mode core_mode;
+       enum arm_state core_state;
 
        /** Flag reporting unavailability of the BKPT instruction. */
        bool is_armv4;
 
+       /** Flag reporting whether semihosting is active. */
+       bool is_semihosting;
+
+       /** Value to be returned by semihosting SYS_ERRNO request. */
+       int semihosting_errno;
+
        /** Backpointer to the target. */
        struct target *target;
 
@@ -116,9 +130,9 @@ struct arm
 
        int (*full_context)(struct target *target);
        int (*read_core_reg)(struct target *target, struct reg *reg,
-                       int num, enum armv4_5_mode mode);
+                       int num, enum arm_mode mode);
        int (*write_core_reg)(struct target *target, struct reg *reg,
-                       int num, enum armv4_5_mode mode, uint32_t value);
+                       int num, enum arm_mode mode, uint32_t value);
 
        /** Read coprocessor register.  */
        int (*mrc)(struct target *target, int cpnum,
@@ -135,8 +149,6 @@ struct arm
        void *arch_info;
 };
 
-#define target_to_armv4_5 target_to_arm
-
 /** Convert target handle to generic ARM target state handle. */
 static inline struct arm *target_to_arm(struct target *target)
 {
@@ -145,21 +157,21 @@ static inline struct arm *target_to_arm(struct target *target)
 
 static inline bool is_arm(struct arm *arm)
 {
-       return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
+       return arm && arm->common_magic == ARM_COMMON_MAGIC;
 }
 
-struct armv4_5_algorithm
+struct arm_algorithm
 {
        int common_magic;
 
-       enum armv4_5_mode core_mode;
-       enum armv4_5_state core_state;
+       enum arm_mode core_mode;
+       enum arm_state core_state;
 };
 
 struct arm_reg
 {
        int num;
-       enum armv4_5_mode mode;
+       enum arm_mode mode;
        struct target *target;
        struct arm *armv4_5_common;
        uint32_t value;