* Copyright (C) 2008 by Oyvind Harboe *
* oyvind.harboe@zylin.com *
* *
+ * Copyright (C) 2018 by Liviu Ionescu *
+ * <ilg@livius.net> *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include <helper/binarybuffer.h>
#include "algorithm.h"
#include "register.h"
+#include "semihosting_common.h"
/* offsets into armv4_5 core register cache */
enum {
ARMV4_5_SPSR_SVC = 34,
ARMV4_5_SPSR_ABT = 35,
ARMV4_5_SPSR_UND = 36,
- ARM_SPSR_MON = 39,
+ ARM_SPSR_MON = 41,
};
static const uint8_t arm_usr_indices[17] = {
};
static const uint8_t arm_mon_indices[3] = {
- 37, 38, ARM_SPSR_MON,
+ 39, 40, ARM_SPSR_MON,
};
static const struct {
.n_indices = ARRAY_SIZE(arm_mon_indices),
.indices = arm_mon_indices,
},
+ {
+ .name = "Secure Monitor ARM1176JZF-S",
+ .psr = ARM_MODE_1176_MON,
+ .n_indices = ARRAY_SIZE(arm_mon_indices),
+ .indices = arm_mon_indices,
+ },
/* These special modes are currently only supported
* by ARMv6M and ARMv7M profiles */
case ARM_MODE_SYS:
return 6;
case ARM_MODE_MON:
+ case ARM_MODE_1176_MON:
return 7;
default:
LOG_ERROR("invalid mode value encountered %d", mode);
* (Exception modes have both CPSR and SPSR registers ...)
*/
unsigned cookie;
+ unsigned gdb_index;
enum arm_mode mode;
} arm_core_regs[] = {
/* IMPORTANT: we guarantee that the first eight cached registers
* correspond to r0..r7, and the fifteenth to PC, so that callers
* don't need to map them.
*/
- { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, },
- { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, },
- { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, },
- { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, },
- { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, },
- { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, },
- { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, },
- { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, },
+ { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
+ { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
+ { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
+ { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
+ { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
+ { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
+ { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
+ { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
/* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
* them as MODE_ANY creates special cases. (ANY means
* "not mapped" elsewhere; here it's "everything but FIQ".)
*/
- { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, },
- { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, },
- { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, },
- { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, },
- { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, },
+ { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
+ { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
+ { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
+ { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
+ { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
+
+ /* Historical GDB mapping of indices:
+ * - 13-14 are sp and lr, but banked counterparts are used
+ * - 16-24 are left for deprecated 8 FPA + 1 FPS
+ * - 25 is the cpsr
+ */
/* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
- { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, },
- { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, },
+ { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
+ { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
/* guaranteed to be at index 15 */
- { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, },
+ { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
+ { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
+ { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
+ { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
+ { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
+ { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
+
+ { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
+ { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
- { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, },
- { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, },
- { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, },
- { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, },
- { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, },
+ { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
+ { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
- { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, },
- { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, },
+ { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
+ { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
- { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, },
- { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, },
+ { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
+ { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
- { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, },
- { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, },
+ { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
+ { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
- { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, },
- { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, },
+ { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
+ { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
+ { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
+ { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
+ { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
+ { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
- { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, },
- { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, },
+ /* These are only used for GDB target description, banked registers are accessed instead */
+ { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
+ { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
- { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, },
- { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, },
- { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, },
- { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, },
- { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, },
- { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, },
+ /* These exist only when the Security Extension (TrustZone) is present */
+ { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
+ { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
+ { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
- { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, },
- { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, },
- { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, },
+};
+
+static const struct {
+ unsigned int id;
+ const char *name;
+ uint32_t bits;
+ enum arm_mode mode;
+ enum reg_type type;
+ const char *group;
+ const char *feature;
+} arm_vfp_v3_regs[] = {
+ { ARM_VFP_V3_D0, "d0", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D1, "d1", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D2, "d2", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D3, "d3", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D4, "d4", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D5, "d5", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D6, "d6", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D7, "d7", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D8, "d8", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D9, "d9", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D10, "d10", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D11, "d11", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D12, "d12", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D13, "d13", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D14, "d14", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D15, "d15", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D16, "d16", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D17, "d17", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D18, "d18", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D19, "d19", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D20, "d20", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D21, "d21", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D22, "d22", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D23, "d23", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D24, "d24", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D25, "d25", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D26, "d26", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D27, "d27", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D28, "d28", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D29, "d29", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D30, "d30", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_D31, "d31", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
+ { ARM_VFP_V3_FPSCR, "fpscr", 32, ARM_MODE_ANY, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp"},
};
/* map core mode (USR, FIQ, ...) and register number to
static const uint8_t arm_gdb_dummy_fp_value[12];
+static struct reg_feature arm_gdb_dummy_fp_features = {
+ .name = "net.sourceforge.openocd.fake_fpa"
+};
+
/**
* Dummy FPA registers are required to support GDB on ARM.
* Register packets require eight obsolete FPA register values.
.value = (uint8_t *) arm_gdb_dummy_fp_value,
.valid = 1,
.size = 96,
+ .exist = false,
+ .number = 16,
+ .feature = &arm_gdb_dummy_fp_features,
+ .group = "fake_fpa",
};
static const uint8_t arm_gdb_dummy_fps_value[4];
.value = (uint8_t *) arm_gdb_dummy_fps_value,
.valid = 1,
.size = 32,
+ .exist = false,
+ .number = 24,
+ .feature = &arm_gdb_dummy_fp_features,
+ .group = "fake_fpa",
};
static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
LOG_DEBUG("changing ARM core mode to '%s'",
arm_mode_name(value & 0x1f));
value &= ~((1 << 24) | (1 << 5));
+ uint8_t t[4];
+ buf_set_u32(t, 0, 32, value);
armv4_5_target->write_core_reg(target, reg,
- 16, ARM_MODE_ANY, value);
+ 16, ARM_MODE_ANY, t);
}
} else {
buf_set_u32(reg->value, 0, 32, value);
+ if (reg->size == 64) {
+ value = buf_get_u32(buf + 4, 0, 32);
+ buf_set_u32(reg->value + 4, 0, 32, value);
+ }
reg->valid = 1;
}
reg->dirty = 1;
struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
{
int num_regs = ARRAY_SIZE(arm_core_regs);
+ int num_core_regs = num_regs;
+ if (arm->arm_vfp_version == ARM_VFP_V3)
+ num_regs += ARRAY_SIZE(arm_vfp_v3_regs);
+
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
cache->reg_list = reg_list;
cache->num_regs = 0;
- for (i = 0; i < num_regs; i++) {
+ for (i = 0; i < num_core_regs; i++) {
/* Skip registers this core doesn't expose */
if (arm_core_regs[i].mode == ARM_MODE_MON
&& arm->core_type != ARM_MODE_MON)
reg_arch_info[i].target = target;
reg_arch_info[i].arm = arm;
- reg_list[i].name = (char *) arm_core_regs[i].name;
+ reg_list[i].name = arm_core_regs[i].name;
+ reg_list[i].number = arm_core_regs[i].gdb_index;
reg_list[i].size = 32;
- reg_list[i].value = ®_arch_info[i].value;
+ reg_list[i].value = reg_arch_info[i].value;
reg_list[i].type = &arm_reg_type;
reg_list[i].arch_info = ®_arch_info[i];
+ reg_list[i].exist = true;
+
+ /* This really depends on the calling convention in use */
+ reg_list[i].caller_save = false;
+
+ /* Registers data type, as used by GDB target description */
+ reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
+ switch (arm_core_regs[i].cookie) {
+ case 13:
+ reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR;
+ break;
+ case 14:
+ case 15:
+ reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR;
+ break;
+ default:
+ reg_list[i].reg_data_type->type = REG_TYPE_UINT32;
+ break;
+ }
+
+ /* let GDB shows banked registers only in "info all-reg" */
+ reg_list[i].feature = malloc(sizeof(struct reg_feature));
+ if (reg_list[i].number <= 15 || reg_list[i].number == 25) {
+ reg_list[i].feature->name = "org.gnu.gdb.arm.core";
+ reg_list[i].group = "general";
+ } else {
+ reg_list[i].feature->name = "net.sourceforge.openocd.banked";
+ reg_list[i].group = "banked";
+ }
+
+ cache->num_regs++;
+ }
+
+ int j;
+ for (i = num_core_regs, j = 0; i < num_regs; i++, j++) {
+ reg_arch_info[i].num = arm_vfp_v3_regs[j].id;
+ reg_arch_info[i].mode = arm_vfp_v3_regs[j].mode;
+ reg_arch_info[i].target = target;
+ reg_arch_info[i].arm = arm;
+
+ reg_list[i].name = arm_vfp_v3_regs[j].name;
+ reg_list[i].number = arm_vfp_v3_regs[j].id;
+ reg_list[i].size = arm_vfp_v3_regs[j].bits;
+ reg_list[i].value = reg_arch_info[i].value;
+ reg_list[i].type = &arm_reg_type;
+ reg_list[i].arch_info = ®_arch_info[i];
+ reg_list[i].exist = true;
+
+ reg_list[i].caller_save = false;
+
+ reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
+ reg_list[i].reg_data_type->type = arm_vfp_v3_regs[j].type;
+
+ reg_list[i].feature = malloc(sizeof(struct reg_feature));
+ reg_list[i].feature->name = arm_vfp_v3_regs[j].feature;
+
+ reg_list[i].group = arm_vfp_v3_regs[j].group;
cache->num_regs++;
}
arm->pc = reg_list + 15;
arm->cpsr = reg_list + ARMV4_5_CPSR;
arm->core_cache = cache;
+
return cache;
}
return ERROR_FAIL;
}
+ /* avoid filling log waiting for fileio reply */
+ if (target->semihosting && target->semihosting->hit_fileio)
+ return ERROR_OK;
+
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
- "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
+ "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s%s",
arm_state_strings[arm->core_state],
debug_reason_name(target),
arm_mode_name(arm->core_mode),
buf_get_u32(arm->cpsr->value, 0, 32),
buf_get_u32(arm->pc->value, 0, 32),
- arm->is_semihosting ? ", semihosting" : "");
+ (target->semihosting && target->semihosting->is_active) ? ", semihosting" : "",
+ (target->semihosting && target->semihosting->is_fileio) ? " fileio" : "");
return ERROR_OK;
}
}
struct arm *arm = target_to_arm(target);
- uint32_t address;
+ target_addr_t address;
int count = 1;
int thumb = 0;
COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
/* FALL THROUGH */
case 1:
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+ COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
if (address & 0x01) {
if (!thumb) {
command_print(CMD_CTX, "Disassemble as Thumb");
return JIM_OK;
}
-COMMAND_HANDLER(handle_arm_semihosting_command)
-{
- struct target *target = get_current_target(CMD_CTX);
-
- if (target == NULL) {
- LOG_ERROR("No target selected");
- return ERROR_FAIL;
- }
-
- struct arm *arm = target_to_arm(target);
-
- if (!is_arm(arm)) {
- command_print(CMD_CTX, "current target isn't an ARM");
- return ERROR_FAIL;
- }
-
- if (!arm->setup_semihosting) {
- command_print(CMD_CTX, "semihosting not supported for current target");
- return ERROR_FAIL;
- }
-
- if (CMD_ARGC > 0) {
- int semihosting;
-
- COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
-
- if (!target_was_examined(target)) {
- LOG_ERROR("Target not examined yet");
- return ERROR_FAIL;
- }
-
- if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
- LOG_ERROR("Failed to Configure semihosting");
- return ERROR_FAIL;
- }
-
- /* FIXME never let that "catch" be dropped! */
- arm->is_semihosting = semihosting;
- }
-
- command_print(CMD_CTX, "semihosting is %s",
- arm->is_semihosting
- ? "enabled" : "disabled");
-
- return ERROR_OK;
-}
+extern __COMMAND_HANDLER(handle_common_semihosting_command);
+extern __COMMAND_HANDLER(handle_common_semihosting_fileio_command);
+extern __COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command);
+extern __COMMAND_HANDLER(handle_common_semihosting_cmdline);
static const struct command_registration arm_exec_command_handlers[] = {
{
},
{
.name = "mrc",
+ .mode = COMMAND_EXEC,
.jim_handler = &jim_mcrmrc,
.help = "read coprocessor register",
.usage = "cpnum op1 CRn CRm op2",
},
{
"semihosting",
- .handler = handle_arm_semihosting_command,
+ .handler = handle_common_semihosting_command,
.mode = COMMAND_EXEC,
.usage = "['enable'|'disable']",
.help = "activate support for semihosting operations",
},
-
+ {
+ "semihosting_cmdline",
+ .handler = handle_common_semihosting_cmdline,
+ .mode = COMMAND_EXEC,
+ .usage = "arguments",
+ .help = "command line arguments to be passed to program",
+ },
+ {
+ "semihosting_fileio",
+ .handler = handle_common_semihosting_fileio_command,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable']",
+ .help = "activate support for semihosting fileio operations",
+ },
+ {
+ "semihosting_resexit",
+ .handler = handle_common_semihosting_resumable_exit_command,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable']",
+ .help = "activate support for semihosting resumable exit",
+ },
COMMAND_REGISTRATION_DONE
};
const struct command_registration arm_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
+/*
+ * gdb for arm targets (e.g. arm-none-eabi-gdb) supports several variants
+ * of arm architecture. You can list them using the autocompletion of gdb
+ * command prompt by typing "set architecture " and then press TAB key.
+ * The default, selected automatically, is "arm".
+ * Let's use the default value, here, to make gdb-multiarch behave in the
+ * same way as a gdb for arm. This can be changed later on. User can still
+ * set the specific architecture variant with the gdb command.
+ */
+const char *arm_get_gdb_arch(struct target *target)
+{
+ return "arm";
+}
+
int arm_get_gdb_reg_list(struct target *target,
struct reg **reg_list[], int *reg_list_size,
enum target_register_class reg_class)
{
struct arm *arm = target_to_arm(target);
- int i;
+ unsigned int i;
if (!is_arm_mode(arm->core_mode)) {
LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
}
- *reg_list_size = 26;
- *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
+ switch (reg_class) {
+ case REG_CLASS_GENERAL:
+ *reg_list_size = 26;
+ *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
- for (i = 0; i < 16; i++)
- (*reg_list)[i] = arm_reg_current(arm, i);
+ for (i = 0; i < 16; i++)
+ (*reg_list)[i] = arm_reg_current(arm, i);
- for (i = 16; i < 24; i++)
- (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
+ /* For GDB compatibility, take FPA registers size into account and zero-fill it*/
+ for (i = 16; i < 24; i++)
+ (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
+ (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
- (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
- (*reg_list)[25] = arm->cpsr;
+ (*reg_list)[25] = arm->cpsr;
- return ERROR_OK;
+ return ERROR_OK;
+ break;
+
+ case REG_CLASS_ALL:
+ *reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
+ unsigned int list_size_core = *reg_list_size;
+ if (arm->arm_vfp_version == ARM_VFP_V3)
+ *reg_list_size += 33;
+
+ *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
+
+ for (i = 0; i < 16; i++)
+ (*reg_list)[i] = arm_reg_current(arm, i);
+
+ for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
+ int reg_index = arm->core_cache->reg_list[i].number;
+ if (!(arm_core_regs[i].mode == ARM_MODE_MON
+ && arm->core_type != ARM_MODE_MON))
+ (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
+ }
+
+ /* When we supply the target description, there is no need for fake FPA */
+ for (i = 16; i < 24; i++) {
+ (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
+ (*reg_list)[i]->size = 0;
+ }
+ (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
+ (*reg_list)[24]->size = 0;
+
+ if (arm->arm_vfp_version == ARM_VFP_V3) {
+ unsigned int num_core_regs = ARRAY_SIZE(arm_core_regs);
+ for (i = 0; i < 33; i++)
+ (*reg_list)[list_size_core + i] = &(arm->core_cache->reg_list[num_core_regs + i]);
+ }
+
+ return ERROR_OK;
+ break;
+
+ default:
+ LOG_ERROR("not a valid register class type in query.");
+ return ERROR_FAIL;
+ break;
+ }
}
/* wait for execution to complete and check exit point */
}
for (i = 0; i < num_reg_params; i++) {
+ if (reg_params[i].direction == PARAM_IN)
+ continue;
+
struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
if (!reg) {
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
struct mem_param *mem_params,
int num_reg_params,
struct reg_param *reg_params,
- uint32_t entry_point,
- uint32_t exit_point,
+ target_addr_t entry_point,
+ target_addr_t exit_point,
int timeout_ms,
void *arch_info)
{
mem_params,
num_reg_params,
reg_params,
- entry_point,
- exit_point,
+ (uint32_t)entry_point,
+ (uint32_t)exit_point,
timeout_ms,
arch_info,
armv4_5_run_algorithm_completion);
*
*/
int arm_checksum_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *checksum)
+ target_addr_t address, uint32_t count, uint32_t *checksum)
{
struct working_area *crc_algorithm;
struct arm_algorithm arm_algo;
uint32_t i;
uint32_t exit_var = 0;
- /* see contrib/loaders/checksum/armv4_5_crc.s for src */
-
- static const uint32_t arm_crc_code[] = {
- 0xE1A02000, /* mov r2, r0 */
- 0xE3E00000, /* mov r0, #0xffffffff */
- 0xE1A03001, /* mov r3, r1 */
- 0xE3A04000, /* mov r4, #0 */
- 0xEA00000B, /* b ncomp */
- /* nbyte: */
- 0xE7D21004, /* ldrb r1, [r2, r4] */
- 0xE59F7030, /* ldr r7, CRC32XOR */
- 0xE0200C01, /* eor r0, r0, r1, asl 24 */
- 0xE3A05000, /* mov r5, #0 */
- /* loop: */
- 0xE3500000, /* cmp r0, #0 */
- 0xE1A06080, /* mov r6, r0, asl #1 */
- 0xE2855001, /* add r5, r5, #1 */
- 0xE1A00006, /* mov r0, r6 */
- 0xB0260007, /* eorlt r0, r6, r7 */
- 0xE3550008, /* cmp r5, #8 */
- 0x1AFFFFF8, /* bne loop */
- 0xE2844001, /* add r4, r4, #1 */
- /* ncomp: */
- 0xE1540003, /* cmp r4, r3 */
- 0x1AFFFFF1, /* bne nbyte */
- /* end: */
- 0xe1200070, /* bkpt #0 */
- /* CRC32XOR: */
- 0x04C11DB7 /* .word 0x04C11DB7 */
+ static const uint8_t arm_crc_code_le[] = {
+#include "../../contrib/loaders/checksum/armv4_5_crc.inc"
};
+ assert(sizeof(arm_crc_code_le) % 4 == 0);
+
retval = target_alloc_working_area(target,
- sizeof(arm_crc_code), &crc_algorithm);
+ sizeof(arm_crc_code_le), &crc_algorithm);
if (retval != ERROR_OK)
return retval;
/* convert code into a buffer in target endianness */
- for (i = 0; i < ARRAY_SIZE(arm_crc_code); i++) {
+ for (i = 0; i < ARRAY_SIZE(arm_crc_code_le) / 4; i++) {
retval = target_write_u32(target,
crc_algorithm->address + i * sizeof(uint32_t),
- arm_crc_code[i]);
+ le_to_h_u32(&arm_crc_code_le[i * 4]));
if (retval != ERROR_OK)
- return retval;
+ goto cleanup;
}
arm_algo.common_magic = ARM_COMMON_MAGIC;
/* armv4 must exit using a hardware breakpoint */
if (arm->is_armv4)
- exit_var = crc_algorithm->address + sizeof(arm_crc_code) - 8;
+ exit_var = crc_algorithm->address + sizeof(arm_crc_code_le) - 8;
retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
crc_algorithm->address,
exit_var,
timeout, &arm_algo);
- if (retval != ERROR_OK) {
- LOG_ERROR("error executing ARM crc algorithm");
- destroy_reg_param(®_params[0]);
- destroy_reg_param(®_params[1]);
- target_free_working_area(target, crc_algorithm);
- return retval;
- }
- *checksum = buf_get_u32(reg_params[0].value, 0, 32);
+ if (retval == ERROR_OK)
+ *checksum = buf_get_u32(reg_params[0].value, 0, 32);
+ else
+ LOG_ERROR("error executing ARM crc algorithm");
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
+cleanup:
target_free_working_area(target, crc_algorithm);
- return ERROR_OK;
+ return retval;
}
/**
*
*/
int arm_blank_check_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *blank)
+ struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
{
struct working_area *check_algorithm;
struct reg_param reg_params[3];
uint32_t i;
uint32_t exit_var = 0;
- /* see contrib/loaders/erase_check/armv4_5_erase_check.s for src */
-
- static const uint32_t check_code[] = {
- /* loop: */
- 0xe4d03001, /* ldrb r3, [r0], #1 */
- 0xe0022003, /* and r2, r2, r3 */
- 0xe2511001, /* subs r1, r1, #1 */
- 0x1afffffb, /* bne loop */
- /* end: */
- 0xe1200070, /* bkpt #0 */
+ static const uint8_t check_code_le[] = {
+#include "../../contrib/loaders/erase_check/armv4_5_erase_check.inc"
};
+ assert(sizeof(check_code_le) % 4 == 0);
+
+ if (erased_value != 0xff) {
+ LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets",
+ erased_value);
+ return ERROR_FAIL;
+ }
+
/* make sure we have a working area */
retval = target_alloc_working_area(target,
- sizeof(check_code), &check_algorithm);
+ sizeof(check_code_le), &check_algorithm);
if (retval != ERROR_OK)
return retval;
/* convert code into a buffer in target endianness */
- for (i = 0; i < ARRAY_SIZE(check_code); i++) {
+ for (i = 0; i < ARRAY_SIZE(check_code_le) / 4; i++) {
retval = target_write_u32(target,
check_algorithm->address
+ i * sizeof(uint32_t),
- check_code[i]);
+ le_to_h_u32(&check_code_le[i * 4]));
if (retval != ERROR_OK)
- return retval;
+ goto cleanup;
}
arm_algo.common_magic = ARM_COMMON_MAGIC;
arm_algo.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
- buf_set_u32(reg_params[0].value, 0, 32, address);
+ buf_set_u32(reg_params[0].value, 0, 32, blocks[0].address);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
- buf_set_u32(reg_params[1].value, 0, 32, count);
+ buf_set_u32(reg_params[1].value, 0, 32, blocks[0].size);
init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
- buf_set_u32(reg_params[2].value, 0, 32, 0xff);
+ buf_set_u32(reg_params[2].value, 0, 32, erased_value);
/* armv4 must exit using a hardware breakpoint */
if (arm->is_armv4)
- exit_var = check_algorithm->address + sizeof(check_code) - 4;
+ exit_var = check_algorithm->address + sizeof(check_code_le) - 4;
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
check_algorithm->address,
exit_var,
10000, &arm_algo);
- if (retval != ERROR_OK) {
- destroy_reg_param(®_params[0]);
- destroy_reg_param(®_params[1]);
- destroy_reg_param(®_params[2]);
- target_free_working_area(target, check_algorithm);
- return retval;
- }
- *blank = buf_get_u32(reg_params[2].value, 0, 32);
+ if (retval == ERROR_OK)
+ blocks[0].result = buf_get_u32(reg_params[2].value, 0, 32);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
+cleanup:
target_free_working_area(target, check_algorithm);
- return ERROR_OK;
+ if (retval != ERROR_OK)
+ return retval;
+
+ return 1; /* only one block has been checked */
}
static int arm_full_context(struct target *target)
projects / fw / openocd / blobdiff