#include "config.h"
#endif
+#include "arm.h"
#include "armv4_5.h"
#include "arm_jtag.h"
#include "breakpoints.h"
#include "arm_disassembler.h"
-#include "binarybuffer.h"
+#include <helper/binarybuffer.h>
#include "algorithm.h"
#include "register.h"
+/* offsets into armv4_5 core register cache */
+enum {
+// ARMV4_5_CPSR = 31,
+ ARMV4_5_SPSR_FIQ = 32,
+ ARMV4_5_SPSR_IRQ = 33,
+ ARMV4_5_SPSR_SVC = 34,
+ ARMV4_5_SPSR_ABT = 35,
+ ARMV4_5_SPSR_UND = 36,
+ ARM_SPSR_MON = 39,
+};
+
static const uint8_t arm_usr_indices[17] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
};
*/
{
.name = "User",
- .psr = ARMV4_5_MODE_USR,
+ .psr = ARM_MODE_USR,
.n_indices = ARRAY_SIZE(arm_usr_indices),
.indices = arm_usr_indices,
},
{
.name = "FIQ",
- .psr = ARMV4_5_MODE_FIQ,
+ .psr = ARM_MODE_FIQ,
.n_indices = ARRAY_SIZE(arm_fiq_indices),
.indices = arm_fiq_indices,
},
{
.name = "Supervisor",
- .psr = ARMV4_5_MODE_SVC,
+ .psr = ARM_MODE_SVC,
.n_indices = ARRAY_SIZE(arm_svc_indices),
.indices = arm_svc_indices,
},
{
.name = "Abort",
- .psr = ARMV4_5_MODE_ABT,
+ .psr = ARM_MODE_ABT,
.n_indices = ARRAY_SIZE(arm_abt_indices),
.indices = arm_abt_indices,
},
{
.name = "IRQ",
- .psr = ARMV4_5_MODE_IRQ,
+ .psr = ARM_MODE_IRQ,
.n_indices = ARRAY_SIZE(arm_irq_indices),
.indices = arm_irq_indices,
},
{
.name = "Undefined instruction",
- .psr = ARMV4_5_MODE_UND,
+ .psr = ARM_MODE_UND,
.n_indices = ARRAY_SIZE(arm_und_indices),
.indices = arm_und_indices,
},
{
.name = "System",
- .psr = ARMV4_5_MODE_SYS,
+ .psr = ARM_MODE_SYS,
.n_indices = ARRAY_SIZE(arm_usr_indices),
.indices = arm_usr_indices,
},
}
/** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
-int armv4_5_mode_to_number(enum armv4_5_mode mode)
+int arm_mode_to_number(enum arm_mode mode)
{
switch (mode) {
- case ARMV4_5_MODE_ANY:
+ case ARM_MODE_ANY:
/* map MODE_ANY to user mode */
- case ARMV4_5_MODE_USR:
+ case ARM_MODE_USR:
return 0;
- case ARMV4_5_MODE_FIQ:
+ case ARM_MODE_FIQ:
return 1;
- case ARMV4_5_MODE_IRQ:
+ case ARM_MODE_IRQ:
return 2;
- case ARMV4_5_MODE_SVC:
+ case ARM_MODE_SVC:
return 3;
- case ARMV4_5_MODE_ABT:
+ case ARM_MODE_ABT:
return 4;
- case ARMV4_5_MODE_UND:
+ case ARM_MODE_UND:
return 5;
- case ARMV4_5_MODE_SYS:
+ case ARM_MODE_SYS:
return 6;
case ARM_MODE_MON:
return 7;
}
/** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
-enum armv4_5_mode armv4_5_number_to_mode(int number)
+enum arm_mode armv4_5_number_to_mode(int number)
{
switch (number) {
case 0:
- return ARMV4_5_MODE_USR;
+ return ARM_MODE_USR;
case 1:
- return ARMV4_5_MODE_FIQ;
+ return ARM_MODE_FIQ;
case 2:
- return ARMV4_5_MODE_IRQ;
+ return ARM_MODE_IRQ;
case 3:
- return ARMV4_5_MODE_SVC;
+ return ARM_MODE_SVC;
case 4:
- return ARMV4_5_MODE_ABT;
+ return ARM_MODE_ABT;
case 5:
- return ARMV4_5_MODE_UND;
+ return ARM_MODE_UND;
case 6:
- return ARMV4_5_MODE_SYS;
+ return ARM_MODE_SYS;
case 7:
return ARM_MODE_MON;
default:
LOG_ERROR("mode index out of bounds %d", number);
- return ARMV4_5_MODE_ANY;
+ return ARM_MODE_ANY;
}
}
-char* armv4_5_state_strings[] =
+static const char *arm_state_strings[] =
{
"ARM", "Thumb", "Jazelle", "ThumbEE",
};
*
* NOTE: offsets in this table are coupled to the arm_mode_data
* table above, the armv4_5_core_reg_map array below, and also to
- * the ARMV4_5_*PSR* symols.
+ * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
*/
static const struct {
/* The name is used for e.g. the "regs" command. */
* (Exception modes have both CPSR and SPSR registers ...)
*/
unsigned cookie;
- enum armv4_5_mode mode;
+ enum arm_mode mode;
} arm_core_regs[] = {
- { .name = "r0", .cookie = 0, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r1", .cookie = 1, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r2", .cookie = 2, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r3", .cookie = 3, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r4", .cookie = 4, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r5", .cookie = 5, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r6", .cookie = 6, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r7", .cookie = 7, .mode = ARMV4_5_MODE_ANY, },
+ /* IMPORTANT: we guarantee that the first eight cached registers
+ * correspond to r0..r7, and the fifteenth to PC, so that callers
+ * don't need to map them.
+ */
+ { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, },
+ { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, },
+ { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, },
+ { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, },
+ { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, },
+ { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, },
+ { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, },
+ { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, },
/* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
- * them as MODE_ANY creates special cases.
+ * them as MODE_ANY creates special cases. (ANY means
+ * "not mapped" elsewhere; here it's "everything but FIQ".)
*/
- { .name = "r8", .cookie = 8, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r9", .cookie = 9, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r10", .cookie = 10, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r11", .cookie = 11, .mode = ARMV4_5_MODE_ANY, },
- { .name = "r12", .cookie = 12, .mode = ARMV4_5_MODE_ANY, },
+ { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, },
+ { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, },
+ { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, },
+ { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, },
+ { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, },
/* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
- { .name = "sp_usr", .cookie = 13, .mode = ARMV4_5_MODE_USR, },
- { .name = "lr_usr", .cookie = 14, .mode = ARMV4_5_MODE_USR, },
+ { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, },
+ { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, },
- { .name = "pc", .cookie = 15, .mode = ARMV4_5_MODE_ANY, },
+ /* guaranteed to be at index 15 */
+ { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, },
- { .name = "r8_fiq", .cookie = 8, .mode = ARMV4_5_MODE_FIQ, },
- { .name = "r9_fiq", .cookie = 9, .mode = ARMV4_5_MODE_FIQ, },
- { .name = "r10_fiq", .cookie = 10, .mode = ARMV4_5_MODE_FIQ, },
- { .name = "r11_fiq", .cookie = 11, .mode = ARMV4_5_MODE_FIQ, },
- { .name = "r12_fiq", .cookie = 12, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, },
+ { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, },
+ { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, },
+ { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, },
+ { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, },
- { .name = "lr_fiq", .cookie = 13, .mode = ARMV4_5_MODE_FIQ, },
- { .name = "sp_fiq", .cookie = 14, .mode = ARMV4_5_MODE_FIQ, },
+ { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, },
+ { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, },
- { .name = "lr_irq", .cookie = 13, .mode = ARMV4_5_MODE_IRQ, },
- { .name = "sp_irq", .cookie = 14, .mode = ARMV4_5_MODE_IRQ, },
+ { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, },
+ { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, },
- { .name = "lr_svc", .cookie = 13, .mode = ARMV4_5_MODE_SVC, },
- { .name = "sp_svc", .cookie = 14, .mode = ARMV4_5_MODE_SVC, },
+ { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, },
+ { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, },
- { .name = "lr_abt", .cookie = 13, .mode = ARMV4_5_MODE_ABT, },
- { .name = "sp_abt", .cookie = 14, .mode = ARMV4_5_MODE_ABT, },
+ { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, },
+ { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, },
- { .name = "lr_und", .cookie = 13, .mode = ARMV4_5_MODE_UND, },
- { .name = "sp_und", .cookie = 14, .mode = ARMV4_5_MODE_UND, },
+ { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, },
+ { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, },
- { .name = "cpsr", .cookie = 16, .mode = ARMV4_5_MODE_ANY, },
- { .name = "spsr_fiq", .cookie = 16, .mode = ARMV4_5_MODE_FIQ, },
- { .name = "spsr_irq", .cookie = 16, .mode = ARMV4_5_MODE_IRQ, },
- { .name = "spsr_svc", .cookie = 16, .mode = ARMV4_5_MODE_SVC, },
- { .name = "spsr_abt", .cookie = 16, .mode = ARMV4_5_MODE_ABT, },
- { .name = "spsr_und", .cookie = 16, .mode = ARMV4_5_MODE_UND, },
+ { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, },
+ { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, },
+ { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, },
+ { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, },
+ { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, },
+ { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, },
- { .name = "lr_mon", .cookie = 13, .mode = ARM_MODE_MON, },
- { .name = "sp_mon", .cookie = 14, .mode = ARM_MODE_MON, },
+ { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, },
+ { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, },
{ .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, },
};
}
};
+/**
+ * Configures host-side ARM records to reflect the specified CPSR.
+ * Later, code can use arm_reg_current() to map register numbers
+ * according to how they are exposed by this mode.
+ */
+void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
+{
+ enum arm_mode mode = cpsr & 0x1f;
+ int num;
+
+ /* NOTE: this may be called very early, before the register
+ * cache is set up. We can't defend against many errors, in
+ * particular against CPSRs that aren't valid *here* ...
+ */
+ if (arm->cpsr) {
+ buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
+ arm->cpsr->valid = 1;
+ arm->cpsr->dirty = 0;
+ }
+
+ arm->core_mode = mode;
+
+ /* mode_to_number() warned; set up a somewhat-sane mapping */
+ num = arm_mode_to_number(mode);
+ if (num < 0) {
+ mode = ARM_MODE_USR;
+ num = 0;
+ }
+
+ arm->map = &armv4_5_core_reg_map[num][0];
+ arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
+ ? NULL
+ : arm->core_cache->reg_list + arm->map[16];
+
+ /* Older ARMs won't have the J bit */
+ enum arm_state state;
+
+ if (cpsr & (1 << 5)) { /* T */
+ if (cpsr & (1 << 24)) { /* J */
+ LOG_WARNING("ThumbEE -- incomplete support");
+ state = ARM_STATE_THUMB_EE;
+ } else
+ state = ARM_STATE_THUMB;
+ } else {
+ if (cpsr & (1 << 24)) { /* J */
+ LOG_ERROR("Jazelle state handling is BROKEN!");
+ state = ARM_STATE_JAZELLE;
+ } else
+ state = ARM_STATE_ARM;
+ }
+ arm->core_state = state;
+
+ LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
+ arm_mode_name(mode),
+ arm_state_strings[arm->core_state]);
+}
+
+/**
+ * Returns handle to the register currently mapped to a given number.
+ * Someone must have called arm_set_cpsr() before.
+ *
+ * \param arm This core's state and registers are used.
+ * \param regnum From 0..15 corresponding to R0..R14 and PC.
+ * Note that R0..R7 don't require mapping; you may access those
+ * as the first eight entries in the register cache. Likewise
+ * R15 (PC) doesn't need mapping; you may also access it directly.
+ * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
+ * CPSR (arm->cpsr) is also not mapped.
+ */
+struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
+{
+ struct reg *r;
+
+ if (regnum > 16)
+ return NULL;
+
+ r = arm->core_cache->reg_list + arm->map[regnum];
+
+ /* e.g. invalid CPSR said "secure monitor" mode on a core
+ * that doesn't support it...
+ */
+ if (!r) {
+ LOG_ERROR("Invalid CPSR mode");
+ r = arm->core_cache->reg_list + regnum;
+ }
+
+ return r;
+}
+
static const uint8_t arm_gdb_dummy_fp_value[12];
/**
{
struct arm_reg *armv4_5 = reg->arch_info;
struct target *target = armv4_5->target;
- struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target);
+ struct arm *armv4_5_target = target_to_arm(target);
uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED)
/* Except for CPSR, the "reg" command exposes a writeback model
* for the register cache.
*/
- buf_set_u32(reg->value, 0, 32, value);
- reg->dirty = 1;
- reg->valid = 1;
+ if (reg == armv4_5_target->cpsr) {
+ arm_set_cpsr(armv4_5_target, value);
- if (reg == &armv4_5_target->core_cache->reg_list[ARMV4_5_CPSR])
- {
- /* FIXME handle J bit too; mostly for ThumbEE, also Jazelle */
- if (value & 0x20)
- {
- /* T bit should be set */
- if (armv4_5_target->core_state == ARMV4_5_STATE_ARM)
- {
- /* change state to Thumb */
- LOG_DEBUG("changing to Thumb state");
- armv4_5_target->core_state = ARMV4_5_STATE_THUMB;
- }
- }
- else
- {
- /* T bit should be cleared */
- if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB)
- {
- /* change state to ARM */
- LOG_DEBUG("changing to ARM state");
- armv4_5_target->core_state = ARMV4_5_STATE_ARM;
- }
- }
-
- /* REVISIT Why only update core for mode change, not also
- * for state changes? Possibly older cores need to stay
- * in ARM mode during halt mode debug, not execute Thumb;
- * v6/v7a/v7r seem to do that automatically...
+ /* Older cores need help to be in ARM mode during halt
+ * mode debug, so we clear the J and T bits if we flush.
+ * For newer cores (v6/v7a/v7r) we don't need that, but
+ * it won't hurt since CPSR is always flushed anyway.
*/
-
- if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f))
- {
+ if (armv4_5_target->core_mode !=
+ (enum arm_mode)(value & 0x1f)) {
LOG_DEBUG("changing ARM core mode to '%s'",
arm_mode_name(value & 0x1f));
- armv4_5_target->core_mode = value & 0x1f;
+ value &= ~((1 << 24) | (1 << 5));
armv4_5_target->write_core_reg(target, reg,
- 16, ARMV4_5_MODE_ANY, value);
- reg->dirty = 0;
+ 16, ARM_MODE_ANY, value);
}
+ } else {
+ buf_set_u32(reg->value, 0, 32, value);
+ reg->valid = 1;
}
+ reg->dirty = 1;
return ERROR_OK;
}
.set = armv4_5_set_core_reg,
};
-struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
+struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
{
int num_regs = ARRAY_SIZE(arm_core_regs);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
{
/* Skip registers this core doesn't expose */
if (arm_core_regs[i].mode == ARM_MODE_MON
- && armv4_5_common->core_type != ARM_MODE_MON)
+ && arm->core_type != ARM_MODE_MON)
continue;
/* REVISIT handle Cortex-M, which only shadows R13/SP */
arch_info[i].num = arm_core_regs[i].cookie;
arch_info[i].mode = arm_core_regs[i].mode;
arch_info[i].target = target;
- arch_info[i].armv4_5_common = armv4_5_common;
+ arch_info[i].armv4_5_common = arm;
reg_list[i].name = (char *) arm_core_regs[i].name;
reg_list[i].size = 32;
cache->num_regs++;
}
- armv4_5_common->core_cache = cache;
+ arm->pc = reg_list + 15;
+ arm->cpsr = reg_list + ARMV4_5_CPSR;
+ arm->core_cache = cache;
return cache;
}
-int armv4_5_arch_state(struct target *target)
+int arm_arch_state(struct target *target)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
- if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+ if (armv4_5->common_magic != ARM_COMMON_MAGIC)
{
- LOG_ERROR("BUG: called for a non-ARMv4/5 target");
+ LOG_ERROR("BUG: called for a non-ARM target");
return ERROR_FAIL;
}
- LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
- armv4_5_state_strings[armv4_5->core_state],
- Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
- arm_mode_name(armv4_5->core_mode),
- buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
- buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+ LOG_USER("target halted in %s state due to %s, current mode: %s\n"
+ "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
+ arm_state_strings[armv4_5->core_state],
+ debug_reason_name(target),
+ arm_mode_name(armv4_5->core_mode),
+ buf_get_u32(armv4_5->cpsr->value, 0, 32),
+ buf_get_u32(armv4_5->pc->value, 0, 32),
+ armv4_5->is_semihosting ? ", semihosting" : "");
return ERROR_OK;
}
COMMAND_HANDLER(handle_armv4_5_reg_command)
{
struct target *target = get_current_target(CMD_CTX);
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
- unsigned num_regs;
+ struct arm *armv4_5 = target_to_arm(target);
struct reg *regs;
if (!is_arm(armv4_5))
return ERROR_FAIL;
}
+ if (armv4_5->core_type != ARM_MODE_ANY)
+ {
+ command_print(CMD_CTX, "Microcontroller Profile not supported - use standard reg cmd");
+ return ERROR_OK;
+ }
+
if (!is_arm_mode(armv4_5->core_mode))
+ {
+ LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
+ }
if (!armv4_5->full_context) {
command_print(CMD_CTX, "error: target doesn't support %s",
return ERROR_FAIL;
}
- num_regs = armv4_5->core_cache->num_regs;
regs = armv4_5->core_cache->reg_list;
for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
/* label this bank of registers (or shadows) */
switch (arm_mode_data[mode].psr) {
- case ARMV4_5_MODE_SYS:
+ case ARM_MODE_SYS:
continue;
- case ARMV4_5_MODE_USR:
+ case ARM_MODE_USR:
name = "System and User";
sep = "";
break;
COMMAND_HANDLER(handle_armv4_5_core_state_command)
{
struct target *target = get_current_target(CMD_CTX);
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
if (!is_arm(armv4_5))
{
return ERROR_FAIL;
}
+ if (armv4_5->core_type == ARM_MODE_THREAD)
+ {
+ /* armv7m not supported */
+ command_print(CMD_CTX, "Unsupported Command");
+ return ERROR_OK;
+ }
+
if (CMD_ARGC > 0)
{
if (strcmp(CMD_ARGV[0], "arm") == 0)
{
- armv4_5->core_state = ARMV4_5_STATE_ARM;
+ armv4_5->core_state = ARM_STATE_ARM;
}
if (strcmp(CMD_ARGV[0], "thumb") == 0)
{
- armv4_5->core_state = ARMV4_5_STATE_THUMB;
+ armv4_5->core_state = ARM_STATE_THUMB;
}
}
- command_print(CMD_CTX, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
+ command_print(CMD_CTX, "core state: %s", arm_state_strings[armv4_5->core_state]);
return ERROR_OK;
}
-COMMAND_HANDLER(handle_armv4_5_disassemble_command)
+COMMAND_HANDLER(handle_arm_disassemble_command)
{
int retval = ERROR_OK;
struct target *target = get_current_target(CMD_CTX);
- struct arm *arm = target ? target_to_arm(target) : NULL;
+
+ if (target == NULL) {
+ LOG_ERROR("No target selected");
+ return ERROR_FAIL;
+ }
+
+ struct arm *arm = target_to_arm(target);
uint32_t address;
int count = 1;
int thumb = 0;
return ERROR_FAIL;
}
+ if (arm->core_type == ARM_MODE_THREAD)
+ {
+ /* armv7m is always thumb mode */
+ thumb = 1;
+ }
+
switch (CMD_ARGC) {
case 3:
if (strcmp(CMD_ARGV[2], "thumb") != 0)
break;
default:
usage:
- command_print(CMD_CTX,
- "usage: arm disassemble <address> [<count> ['thumb']]");
count = 0;
- retval = ERROR_FAIL;
+ retval = ERROR_COMMAND_SYNTAX_ERROR;
}
while (count-- > 0) {
return retval;
}
-int armv4_5_register_commands(struct command_context *cmd_ctx)
+static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
{
- struct command *armv4_5_cmd;
-
- armv4_5_cmd = register_command(cmd_ctx, NULL, "arm",
- NULL, COMMAND_ANY,
- "generic ARM commands");
-
- register_command(cmd_ctx, armv4_5_cmd, "reg",
- handle_armv4_5_reg_command, COMMAND_EXEC,
- "display ARM core registers");
- register_command(cmd_ctx, armv4_5_cmd, "core_state",
- handle_armv4_5_core_state_command, COMMAND_EXEC,
- "display/change ARM core state <arm | thumb>");
- register_command(cmd_ctx, armv4_5_cmd, "disassemble",
- handle_armv4_5_disassemble_command, COMMAND_EXEC,
- "disassemble instructions "
- "<address> [<count> ['thumb']]");
+ struct command_context *context;
+ struct target *target;
+ struct arm *arm;
+ int retval;
+
+ context = current_command_context(interp);
+ assert( context != NULL);
+
+ target = get_current_target(context);
+ if (target == NULL) {
+ LOG_ERROR("%s: no current target", __func__);
+ return JIM_ERR;
+ }
+ if (!target_was_examined(target)) {
+ LOG_ERROR("%s: not yet examined", target_name(target));
+ return JIM_ERR;
+ }
+ arm = target_to_arm(target);
+ if (!is_arm(arm)) {
+ LOG_ERROR("%s: not an ARM", target_name(target));
+ return JIM_ERR;
+ }
+
+ if ((argc < 6) || (argc > 7)) {
+ /* FIXME use the command name to verify # params... */
+ LOG_ERROR("%s: wrong number of arguments", __func__);
+ return JIM_ERR;
+ }
+
+ int cpnum;
+ uint32_t op1;
+ uint32_t op2;
+ uint32_t CRn;
+ uint32_t CRm;
+ uint32_t value;
+ long l;
+
+ /* NOTE: parameter sequence matches ARM instruction set usage:
+ * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
+ * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
+ * The "rX" is necessarily omitted; it uses Tcl mechanisms.
+ */
+ retval = Jim_GetLong(interp, argv[1], &l);
+ if (retval != JIM_OK)
+ return retval;
+ if (l & ~0xf) {
+ LOG_ERROR("%s: %s %d out of range", __func__,
+ "coprocessor", (int) l);
+ return JIM_ERR;
+ }
+ cpnum = l;
+
+ retval = Jim_GetLong(interp, argv[2], &l);
+ if (retval != JIM_OK)
+ return retval;
+ if (l & ~0x7) {
+ LOG_ERROR("%s: %s %d out of range", __func__,
+ "op1", (int) l);
+ return JIM_ERR;
+ }
+ op1 = l;
+
+ retval = Jim_GetLong(interp, argv[3], &l);
+ if (retval != JIM_OK)
+ return retval;
+ if (l & ~0xf) {
+ LOG_ERROR("%s: %s %d out of range", __func__,
+ "CRn", (int) l);
+ return JIM_ERR;
+ }
+ CRn = l;
+
+ retval = Jim_GetLong(interp, argv[4], &l);
+ if (retval != JIM_OK)
+ return retval;
+ if (l & ~0xf) {
+ LOG_ERROR("%s: %s %d out of range", __func__,
+ "CRm", (int) l);
+ return JIM_ERR;
+ }
+ CRm = l;
+
+ retval = Jim_GetLong(interp, argv[5], &l);
+ if (retval != JIM_OK)
+ return retval;
+ if (l & ~0x7) {
+ LOG_ERROR("%s: %s %d out of range", __func__,
+ "op2", (int) l);
+ return JIM_ERR;
+ }
+ op2 = l;
+
+ value = 0;
+
+ /* FIXME don't assume "mrc" vs "mcr" from the number of params;
+ * that could easily be a typo! Check both...
+ *
+ * FIXME change the call syntax here ... simplest to just pass
+ * the MRC() or MCR() instruction to be executed. That will also
+ * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
+ * if that's ever needed.
+ */
+ if (argc == 7) {
+ retval = Jim_GetLong(interp, argv[6], &l);
+ if (retval != JIM_OK) {
+ return retval;
+ }
+ value = l;
+
+ /* NOTE: parameters reordered! */
+ // ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2)
+ retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
+ if (retval != ERROR_OK)
+ return JIM_ERR;
+ } else {
+ /* NOTE: parameters reordered! */
+ // ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2)
+ retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
+ if (retval != ERROR_OK)
+ return JIM_ERR;
+
+ Jim_SetResult(interp, Jim_NewIntObj(interp, value));
+ }
+
+ return JIM_OK;
+}
+
+COMMAND_HANDLER(handle_arm_semihosting_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+
+ if (target == NULL) {
+ LOG_ERROR("No target selected");
+ return ERROR_FAIL;
+ }
+
+ struct arm *arm = target_to_arm(target);
+
+ if (!is_arm(arm)) {
+ command_print(CMD_CTX, "current target isn't an ARM");
+ return ERROR_FAIL;
+ }
+
+ if (!arm->setup_semihosting)
+ {
+ command_print(CMD_CTX, "semihosting not supported for current target");
+ return ERROR_FAIL;
+ }
+
+ if (CMD_ARGC > 0)
+ {
+ int semihosting;
+
+ COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
+
+ if (!target_was_examined(target))
+ {
+ LOG_ERROR("Target not examined yet");
+ return ERROR_FAIL;
+ }
+
+ if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
+ LOG_ERROR("Failed to Configure semihosting");
+ return ERROR_FAIL;
+ }
+
+ /* FIXME never let that "catch" be dropped! */
+ arm->is_semihosting = semihosting;
+ }
+
+ command_print(CMD_CTX, "semihosting is %s",
+ arm->is_semihosting
+ ? "enabled" : "disabled");
return ERROR_OK;
}
-int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
+static const struct command_registration arm_exec_command_handlers[] = {
+ {
+ .name = "reg",
+ .handler = handle_armv4_5_reg_command,
+ .mode = COMMAND_EXEC,
+ .help = "display ARM core registers",
+ .usage = "",
+ },
+ {
+ .name = "core_state",
+ .handler = handle_armv4_5_core_state_command,
+ .mode = COMMAND_EXEC,
+ .usage = "['arm'|'thumb']",
+ .help = "display/change ARM core state",
+ },
+ {
+ .name = "disassemble",
+ .handler = handle_arm_disassemble_command,
+ .mode = COMMAND_EXEC,
+ .usage = "address [count ['thumb']]",
+ .help = "disassemble instructions ",
+ },
+ {
+ .name = "mcr",
+ .mode = COMMAND_EXEC,
+ .jim_handler = &jim_mcrmrc,
+ .help = "write coprocessor register",
+ .usage = "cpnum op1 CRn op2 CRm value",
+ },
+ {
+ .name = "mrc",
+ .jim_handler = &jim_mcrmrc,
+ .help = "read coprocessor register",
+ .usage = "cpnum op1 CRn op2 CRm",
+ },
+ {
+ "semihosting",
+ .handler = handle_arm_semihosting_command,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable']",
+ .help = "activate support for semihosting operations",
+ },
+
+ COMMAND_REGISTRATION_DONE
+};
+const struct command_registration arm_command_handlers[] = {
+ {
+ .name = "arm",
+ .mode = COMMAND_ANY,
+ .help = "ARM command group",
+ .usage = "",
+ .chain = arm_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+int arm_get_gdb_reg_list(struct target *target,
+ struct reg **reg_list[], int *reg_list_size)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
int i;
if (!is_arm_mode(armv4_5->core_mode))
+ {
+ LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
+ }
*reg_list_size = 26;
*reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
for (i = 0; i < 16; i++)
- {
- (*reg_list)[i] = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i);
- }
+ (*reg_list)[i] = arm_reg_current(armv4_5, i);
for (i = 16; i < 24; i++)
- {
(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
- }
(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
- (*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR];
+ (*reg_list)[25] = armv4_5->cpsr;
return ERROR_OK;
}
static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
{
int retval;
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
{
}
/* fast exit: ARMv5+ code can use BKPT */
- if (exit_point && buf_get_u32(armv4_5->core_cache->reg_list[15].value,
- 0, 32) != exit_point)
+ if (exit_point && buf_get_u32(armv4_5->pc->value, 0, 32) != exit_point)
{
LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
- buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+ buf_get_u32(armv4_5->pc->value, 0, 32));
return ERROR_TARGET_TIMEOUT;
}
return ERROR_OK;
}
-int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info))
+int armv4_5_run_algorithm_inner(struct target *target,
+ int num_mem_params, struct mem_param *mem_params,
+ int num_reg_params, struct reg_param *reg_params,
+ uint32_t entry_point, uint32_t exit_point,
+ int timeout_ms, void *arch_info,
+ int (*run_it)(struct target *target, uint32_t exit_point,
+ int timeout_ms, void *arch_info))
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
- struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
- enum armv4_5_state core_state = armv4_5->core_state;
- enum armv4_5_mode core_mode = armv4_5->core_mode;
+ struct arm *armv4_5 = target_to_arm(target);
+ struct arm_algorithm *arm_algorithm_info = arch_info;
+ enum arm_state core_state = armv4_5->core_state;
uint32_t context[17];
uint32_t cpsr;
int exit_breakpoint_size = 0;
int i;
int retval = ERROR_OK;
+
LOG_DEBUG("Running algorithm");
- if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
+ if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC)
{
LOG_ERROR("current target isn't an ARMV4/5 target");
return ERROR_TARGET_INVALID;
}
if (!is_arm_mode(armv4_5->core_mode))
+ {
+ LOG_ERROR("not a valid arm core mode - communication failure?");
return ERROR_FAIL;
+ }
/* armv5 and later can terminate with BKPT instruction; less overhead */
if (!exit_point && armv4_5->is_armv4)
return ERROR_FAIL;
}
+ /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
+ * they'll be restored later.
+ */
for (i = 0; i <= 16; i++)
{
struct reg *r;
r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5_algorithm_info->core_mode, i);
+ arm_algorithm_info->core_mode, i);
if (!r->valid)
armv4_5->read_core_reg(target, r, i,
- armv4_5_algorithm_info->core_mode);
+ arm_algorithm_info->core_mode);
context[i] = buf_get_u32(r->value, 0, 32);
}
- cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32);
+ cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
for (i = 0; i < num_mem_params; i++)
{
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
- return ERROR_INVALID_ARGUMENTS;
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
if (reg->size != reg_params[i].size)
{
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
- return ERROR_INVALID_ARGUMENTS;
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
if ((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
}
}
- armv4_5->core_state = armv4_5_algorithm_info->core_state;
- if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+ armv4_5->core_state = arm_algorithm_info->core_state;
+ if (armv4_5->core_state == ARM_STATE_ARM)
exit_breakpoint_size = 4;
- else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+ else if (armv4_5->core_state == ARM_STATE_THUMB)
exit_breakpoint_size = 2;
else
{
LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
- return ERROR_INVALID_ARGUMENTS;
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
- if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
+ if (arm_algorithm_info->core_mode != ARM_MODE_ANY)
{
- LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode);
- buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode);
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
+ LOG_DEBUG("setting core_mode: 0x%2.2x",
+ arm_algorithm_info->core_mode);
+ buf_set_u32(armv4_5->cpsr->value, 0, 5,
+ arm_algorithm_info->core_mode);
+ armv4_5->cpsr->dirty = 1;
+ armv4_5->cpsr->valid = 1;
}
/* terminate using a hardware or (ARMv5+) software breakpoint */
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
- retval = ERROR_INVALID_ARGUMENTS;
+ retval = ERROR_COMMAND_SYNTAX_ERROR;
continue;
}
if (reg->size != reg_params[i].size)
{
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
- retval = ERROR_INVALID_ARGUMENTS;
+ retval = ERROR_COMMAND_SYNTAX_ERROR;
continue;
}
}
}
+ /* restore everything we saved before (17 or 18 registers) */
for (i = 0; i <= 16; i++)
{
uint32_t regvalue;
- regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
+ regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).value, 0, 32);
if (regvalue != context[i])
{
- LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
+ LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).name, context[i]);
+ buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).valid = 1;
+ ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).dirty = 1;
}
}
- buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
- armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
+
+ arm_set_cpsr(armv4_5, cpsr);
+ armv4_5->cpsr->dirty = 1;
armv4_5->core_state = core_state;
- armv4_5->core_mode = core_mode;
return retval;
}
/**
* Runs ARM code in the target to calculate a CRC32 checksum.
*
- * \todo On ARMv5+, rely on BKPT termination for reduced overhead.
*/
int arm_checksum_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *checksum)
{
struct working_area *crc_algorithm;
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
+ struct arm *armv4_5 = target_to_arm(target);
struct reg_param reg_params[2];
int retval;
uint32_t i;
+ uint32_t exit_var = 0;
+
+ /* see contib/loaders/checksum/armv4_5_crc.s for src */
static const uint32_t arm_crc_code[] = {
0xE1A02000, /* mov r2, r0 */
0xE1540003, /* cmp r4, r3 */
0x1AFFFFF1, /* bne nbyte */
/* end: */
- 0xEAFFFFFE, /* b end */
+ 0xe1200070, /* bkpt #0 */
/* CRC32XOR: */
0x04C11DB7 /* .word 0x04C11DB7 */
};
return retval;
}
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
- armv4_5_info.core_state = ARMV4_5_STATE_ARM;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
+ armv4_5_info.core_mode = ARM_MODE_SVC;
+ armv4_5_info.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
/* 20 second timeout/megabyte */
int timeout = 20000 * (1 + (count / (1024 * 1024)));
+ /* armv4 must exit using a hardware breakpoint */
+ if (armv4_5->is_armv4)
+ exit_var = crc_algorithm->address + sizeof(arm_crc_code) - 8;
+
retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
crc_algorithm->address,
- crc_algorithm->address + sizeof(arm_crc_code) - 8,
+ exit_var,
timeout, &armv4_5_info);
if (retval != ERROR_OK) {
LOG_ERROR("error executing ARM crc algorithm");
* all ones. NOR flash which has been erased, and thus may be written,
* holds all ones.
*
- * \todo On ARMv5+, rely on BKPT termination for reduced overhead.
*/
int arm_blank_check_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *blank)
{
struct working_area *check_algorithm;
struct reg_param reg_params[3];
- struct armv4_5_algorithm armv4_5_info;
+ struct arm_algorithm armv4_5_info;
+ struct arm *armv4_5 = target_to_arm(target);
int retval;
uint32_t i;
+ uint32_t exit_var = 0;
static const uint32_t check_code[] = {
/* loop: */
0xe2511001, /* subs r1, r1, #1 */
0x1afffffb, /* bne loop */
/* end: */
- 0xeafffffe /* b end */
+ 0xe1200070, /* bkpt #0 */
};
/* make sure we have a working area */
return retval;
}
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
- armv4_5_info.core_state = ARMV4_5_STATE_ARM;
+ armv4_5_info.common_magic = ARM_COMMON_MAGIC;
+ armv4_5_info.core_mode = ARM_MODE_SVC;
+ armv4_5_info.core_state = ARM_STATE_ARM;
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
buf_set_u32(reg_params[0].value, 0, 32, address);
init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
buf_set_u32(reg_params[2].value, 0, 32, 0xff);
+ /* armv4 must exit using a hardware breakpoint */
+ if (armv4_5->is_armv4)
+ exit_var = check_algorithm->address + sizeof(check_code) - 4;
+
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
check_algorithm->address,
- check_algorithm->address + sizeof(check_code) - 4,
+ exit_var,
10000, &armv4_5_info);
if (retval != ERROR_OK) {
destroy_reg_param(®_params[0]);
static int arm_full_context(struct target *target)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *armv4_5 = target_to_arm(target);
unsigned num_regs = armv4_5->core_cache->num_regs;
struct reg *reg = armv4_5->core_cache->reg_list;
int retval = ERROR_OK;
return retval;
}
-int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
+static int arm_default_mrc(struct target *target, int cpnum,
+ uint32_t op1, uint32_t op2,
+ uint32_t CRn, uint32_t CRm,
+ uint32_t *value)
+{
+ LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
+ return ERROR_FAIL;
+}
+
+static int arm_default_mcr(struct target *target, int cpnum,
+ uint32_t op1, uint32_t op2,
+ uint32_t CRn, uint32_t CRm,
+ uint32_t value)
+{
+ LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
+ return ERROR_FAIL;
+}
+
+int arm_init_arch_info(struct target *target, struct arm *armv4_5)
{
target->arch_info = armv4_5;
+ armv4_5->target = target;
- armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5->core_state = ARMV4_5_STATE_ARM;
- armv4_5->core_mode = ARMV4_5_MODE_USR;
+ armv4_5->common_magic = ARM_COMMON_MAGIC;
/* core_type may be overridden by subtype logic */
- armv4_5->core_type = ARMV4_5_MODE_ANY;
+ if (armv4_5->core_type != ARM_MODE_THREAD) {
+ armv4_5->core_type = ARM_MODE_ANY;
+ arm_set_cpsr(armv4_5, ARM_MODE_USR);
+ }
/* default full_context() has no core-specific optimizations */
if (!armv4_5->full_context && armv4_5->read_core_reg)
armv4_5->full_context = arm_full_context;
+ if (!armv4_5->mrc)
+ armv4_5->mrc = arm_default_mrc;
+ if (!armv4_5->mcr)
+ armv4_5->mcr = arm_default_mcr;
+
return ERROR_OK;
}
projects / fw / openocd / blobdiff