target/semihosting: export semihosting_common_handlers[] from header file

[fw/openocd] / src / target / armv4_5.c

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 7da28e349d95eb999bda92305c757a4c62880803..2b347924fed12432b3b13c1207686873414b584b 100644 (file)
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 /***************************************************************************
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
@@ -10,19 +12,6 @@
  *                                                                         *
  *   Copyright (C) 2018 by Liviu Ionescu                                   *
  *   <ilg@livius.net>                                                      *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -856,6 +845,9 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
                char *sep = "\n";
                char *shadow = "";
 
+               if (!arm_mode_data[mode].n_indices)
+                       continue;
+
                /* label this bank of registers (or shadows) */
                switch (arm_mode_data[mode].psr) {
                        case ARM_MODE_SYS:
@@ -869,6 +861,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
                                        continue;
                        /* FALLTHROUGH */
                        case ARM_MODE_MON:
+                       case ARM_MODE_1176_MON:
                                if (arm->core_type != ARM_CORE_TYPE_SEC_EXT
                                        && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
                                        continue;
@@ -945,7 +938,7 @@ COMMAND_HANDLER(handle_arm_disassemble_command)
 #if HAVE_CAPSTONE
        struct target *target = get_current_target(CMD_CTX);
 
-       if (target == NULL) {
+       if (!target) {
                LOG_ERROR("No target selected");
                return ERROR_FAIL;
        }
@@ -1003,10 +996,10 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
        int retval;
 
        context = current_command_context(interp);
-       assert(context != NULL);
+       assert(context);
 
        target = get_current_target(context);
-       if (target == NULL) {
+       if (!target) {
                LOG_ERROR("%s: no current target", __func__);
                return JIM_ERR;
        }
@@ -1029,8 +1022,8 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
        int cpnum;
        uint32_t op1;
        uint32_t op2;
-       uint32_t CRn;
-       uint32_t CRm;
+       uint32_t crn;
+       uint32_t crm;
        uint32_t value;
        long l;
 
@@ -1067,7 +1060,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
                        "CRn", (int) l);
                return JIM_ERR;
        }
-       CRn = l;
+       crn = l;
 
        retval = Jim_GetLong(interp, argv[4], &l);
        if (retval != JIM_OK)
@@ -1077,7 +1070,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
                        "CRm", (int) l);
                return JIM_ERR;
        }
-       CRm = l;
+       crm = l;
 
        retval = Jim_GetLong(interp, argv[5], &l);
        if (retval != JIM_OK)
@@ -1106,14 +1099,14 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
                value = l;
 
                /* NOTE: parameters reordered! */
-               /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
-               retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
+               /* ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2) */
+               retval = arm->mcr(target, cpnum, op1, op2, crn, crm, value);
                if (retval != ERROR_OK)
                        return JIM_ERR;
        } else {
                /* NOTE: parameters reordered! */
-               /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
-               retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
+               /* ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2) */
+               retval = arm->mrc(target, cpnum, op1, op2, crn, crm, &value);
                if (retval != ERROR_OK)
                        return JIM_ERR;
 
@@ -1123,8 +1116,6 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
        return JIM_OK;
 }
 
-extern const struct command_registration semihosting_common_handlers[];
-
 static const struct command_registration arm_exec_command_handlers[] = {
        {
                .name = "reg",
@@ -1145,7 +1136,7 @@ static const struct command_registration arm_exec_command_handlers[] = {
                .handler = handle_arm_disassemble_command,
                .mode = COMMAND_EXEC,
                .usage = "address [count ['thumb']]",
-               .help = "disassemble instructions ",
+               .help = "disassemble instructions",
        },
        {
                .name = "mcr",
@@ -1343,7 +1334,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
        }
 
        /* armv5 and later can terminate with BKPT instruction; less overhead */
-       if (!exit_point && arm->is_armv4) {
+       if (!exit_point && arm->arch == ARM_ARCH_V4) {
                LOG_ERROR("ARMv4 target needs HW breakpoint location");
                return ERROR_FAIL;
        }
@@ -1376,7 +1367,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
                if (reg_params[i].direction == PARAM_IN)
                        continue;
 
-               struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
+               struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, false);
                if (!reg) {
                        LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
                        return ERROR_COMMAND_SYNTAX_ERROR;
@@ -1448,7 +1439,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
 
                        struct reg *reg = register_get_by_name(arm->core_cache,
                                        reg_params[i].reg_name,
-                                       0);
+                                       false);
                        if (!reg) {
                                LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
                                retval = ERROR_COMMAND_SYNTAX_ERROR;
@@ -1564,7 +1555,7 @@ int arm_checksum_memory(struct target *target,
        int timeout = 20000 * (1 + (count / (1024 * 1024)));
 
        /* armv4 must exit using a hardware breakpoint */
-       if (arm->is_armv4)
+       if (arm->arch == ARM_ARCH_V4)
                exit_var = crc_algorithm->address + sizeof(arm_crc_code_le) - 8;
 
        retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
@@ -1645,7 +1636,7 @@ int arm_blank_check_memory(struct target *target,
        buf_set_u32(reg_params[2].value, 0, 32, erased_value);
 
        /* armv4 must exit using a hardware breakpoint */
-       if (arm->is_armv4)
+       if (arm->arch == ARM_ARCH_V4)
                exit_var = check_algorithm->address + sizeof(check_code_le) - 4;
 
        retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
@@ -1677,7 +1668,7 @@ static int arm_full_context(struct target *target)
        int retval = ERROR_OK;
 
        for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
-               if (reg->valid)
+               if (!reg->exist || reg->valid)
                        continue;
                retval = armv4_5_get_core_reg(reg);
        }
@@ -1686,7 +1677,7 @@ static int arm_full_context(struct target *target)
 
 static int arm_default_mrc(struct target *target, int cpnum,
        uint32_t op1, uint32_t op2,
-       uint32_t CRn, uint32_t CRm,
+       uint32_t crn, uint32_t crm,
        uint32_t *value)
 {
        LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
@@ -1695,7 +1686,7 @@ static int arm_default_mrc(struct target *target, int cpnum,
 
 static int arm_default_mcr(struct target *target, int cpnum,
        uint32_t op1, uint32_t op2,
-       uint32_t CRn, uint32_t CRm,
+       uint32_t crn, uint32_t crm,
        uint32_t value)
 {
        LOG_ERROR("%s doesn't implement MCR", target_type_name(target));