Transform 'u8' to 'uint8_t' in src/target

[fw/openocd] / src / target / armv4_5.c

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 1144c7f12508f5636dd9756b292e838336fe937c..1b611bae7abcb71c0d6ff7c5ca2a0c4c60f7b0f8 100644 (file)
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -27,21 +27,10 @@
 #include "config.h"
 #endif
 
-#include "replacements.h"
-
-#include "arm_disassembler.h"
-
 #include "armv4_5.h"
-
-#include "target.h"
-#include "register.h"
-#include "log.h"
+#include "arm_disassembler.h"
 #include "binarybuffer.h"
-#include "command.h"
 
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
 
 bitfield_desc_t armv4_5_psr_bitfield_desc[] =
 {
@@ -164,14 +153,14 @@ int armv4_5_core_reg_map[7][17] =
        }
 };
 
-u8 armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+uint8_t armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 
 reg_t armv4_5_gdb_dummy_fp_reg =
 {
        "GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
 };
 
-u8 armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
+uint8_t armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
 
 reg_t armv4_5_gdb_dummy_fps_reg =
 {
@@ -196,7 +185,7 @@ int armv4_5_get_core_reg(reg_t *reg)
        return retval;
 }
 
-int armv4_5_set_core_reg(reg_t *reg, u8 *buf)
+int armv4_5_set_core_reg(reg_t *reg, uint8_t *buf)
 {
        armv4_5_core_reg_t *armv4_5 = reg->arch_info;
        target_t *target = armv4_5->target;
@@ -353,7 +342,7 @@ int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, cha
                        output_len += snprintf(output + output_len, 128 - output_len, "%8s: %8.8x ", ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
                                buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
                }
-               command_print(cmd_ctx, output);
+               command_print(cmd_ctx, "%s", output);
        }
        command_print(cmd_ctx, "    cpsr: %8.8x spsr_fiq: %8.8x spsr_irq: %8.8x spsr_svc: %8.8x spsr_abt: %8.8x spsr_und: %8.8x",
                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),