Fix logically inverted comment

[fw/openocd] / src / target / armv4_5.c

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index cf0632f1ac6fc530372b9bfe81d8fb3e9eb3c47e..14aec0198c805bbd27b05721966d1a9255ca08a4 100644 (file)
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -27,21 +27,10 @@
 #include "config.h"
 #endif
 
-#include "replacements.h"
-
-#include "arm_disassembler.h"
-
 #include "armv4_5.h"
-
-#include "target.h"
-#include "register.h"
-#include "log.h"
+#include "arm_disassembler.h"
 #include "binarybuffer.h"
-#include "command.h"
 
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
 
 bitfield_desc_t armv4_5_psr_bitfield_desc[] =
 {
@@ -231,7 +220,7 @@ int armv4_5_set_core_reg(reg_t *reg, u8 *buf)
                        }
                }
 
-               if (armv4_5_target->core_mode != (value & 0x1f))
+               if (armv4_5_target->core_mode != (enum armv4_5_mode)(value & 0x1f))
                {
                        LOG_DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]);
                        armv4_5_target->core_mode = value & 0x1f;
@@ -428,23 +417,23 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
 
        for (i = 0; i < count; i++)
        {
-               if(thumb)
+               if (thumb)
                {
-                       if((retval = target_read_u16(target, address, &thumb_opcode)) != ERROR_OK)
+                       if ((retval = target_read_u16(target, address, &thumb_opcode)) != ERROR_OK)
                        {
                                return retval;
                        }
-                       if((retval = thumb_evaluate_opcode(thumb_opcode, address, &cur_instruction)) != ERROR_OK)
+                       if ((retval = thumb_evaluate_opcode(thumb_opcode, address, &cur_instruction)) != ERROR_OK)
                        {
                                return retval;
                        }
                }
                else {
-                       if((retval = target_read_u32(target, address, &opcode)) != ERROR_OK)
+                       if ((retval = target_read_u32(target, address, &opcode)) != ERROR_OK)
                        {
                                return retval;
                        }
-                       if((retval = arm_evaluate_opcode(opcode, address, &cur_instruction)) != ERROR_OK)
+                       if ((retval = arm_evaluate_opcode(opcode, address, &cur_instruction)) != ERROR_OK)
                        {
                                return retval;
                        }
@@ -502,7 +491,7 @@ static int armv4_5_run_algorithm_completion(struct target_s *target, u32 exit_po
        int retval;
        armv4_5_common_t *armv4_5 = target->arch_info;
 
-       if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
+       if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
        {
                return retval;
        }
@@ -564,7 +553,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 
        for (i = 0; i < num_mem_params; i++)
        {
-               if((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+               if ((retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
                {
                        return retval;
                }
@@ -585,7 +574,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
                        exit(-1);
                }
 
-               if((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
+               if ((retval = armv4_5_set_core_reg(reg, reg_params[i].value)) != ERROR_OK)
                {
                        return retval;
                }
@@ -616,7 +605,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
                return ERROR_TARGET_FAILURE;
        }
 
-       if((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
+       if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
        {
                return retval;
        }
@@ -631,7 +620,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
        for (i = 0; i < num_mem_params; i++)
        {
                if (mem_params[i].direction != PARAM_OUT)
-                       if((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+                       if ((retvaltemp = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
                        {
                                        retval = retvaltemp;
                        }
@@ -661,10 +650,15 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 
        for (i = 0; i <= 16; i++)
        {
-               LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
-               buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
-               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
-               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
+               u32 regvalue;
+               regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
+               if (regvalue != context[i])
+               {
+                       LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
+                       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
+                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
+               }
        }
        buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
        armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;