#include "config.h"
#endif
+#include "arm.h"
#include "armv4_5.h"
#include "arm_disassembler.h"
#include "arm_simulator.h"
-#include "binarybuffer.h"
+#include <helper/binarybuffer.h>
#include "register.h"
-#include "log.h"
+#include <helper/log.h>
static uint32_t arm_shift(uint8_t shift, uint32_t Rm,
uint32_t return_value;
int instruction_size;
- if (sim->get_state(sim) == ARMV4_5_STATE_ARM)
+ if (sim->get_state(sim) == ARM_STATE_ARM)
instruction_size = 4;
else
instruction_size = 2;
* if the dry_run_pc argument is provided, no state is changed,
* but the new pc is stored in the variable pointed at by the argument
*/
-int arm_simulate_step_core(struct target *target,
+static int arm_simulate_step_core(struct target *target,
uint32_t *dry_run_pc, struct arm_sim_interface *sim)
{
uint32_t current_pc = sim->get_reg(sim, 15);
int instruction_size;
int retval = ERROR_OK;
- if (sim->get_state(sim) == ARMV4_5_STATE_ARM)
+ if (sim->get_state(sim) == ARM_STATE_ARM)
{
uint32_t opcode;
/* branch instructions */
if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX))
{
- uint32_t target;
+ uint32_t target_address;
if (instruction.info.b_bl_bx_blx.reg_operand == -1)
{
- target = instruction.info.b_bl_bx_blx.target_address;
+ target_address = instruction.info.b_bl_bx_blx.target_address;
}
else
{
- target = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand);
+ target_address = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand);
if (instruction.info.b_bl_bx_blx.reg_operand == 15)
{
- target += 2 * instruction_size;
+ target_address += 2 * instruction_size;
}
}
if (dry_run_pc)
{
- *dry_run_pc = target & ~1;
+ *dry_run_pc = target_address & ~1;
return ERROR_OK;
}
else
{
if (instruction.type == ARM_B)
{
- sim->set_reg(sim, 15, target);
+ sim->set_reg(sim, 15, target_address);
}
else if (instruction.type == ARM_BL)
{
uint32_t old_pc = sim->get_reg(sim, 15);
- int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB);
+ int T = (sim->get_state(sim) == ARM_STATE_THUMB);
sim->set_reg_mode(sim, 14, old_pc + 4 + T);
- sim->set_reg(sim, 15, target);
+ sim->set_reg(sim, 15, target_address);
}
else if (instruction.type == ARM_BX)
{
- if (target & 0x1)
+ if (target_address & 0x1)
{
- sim->set_state(sim, ARMV4_5_STATE_THUMB);
+ sim->set_state(sim, ARM_STATE_THUMB);
}
else
{
- sim->set_state(sim, ARMV4_5_STATE_ARM);
+ sim->set_state(sim, ARM_STATE_ARM);
}
- sim->set_reg(sim, 15, target & 0xfffffffe);
+ sim->set_reg(sim, 15, target_address & 0xfffffffe);
}
else if (instruction.type == ARM_BLX)
{
uint32_t old_pc = sim->get_reg(sim, 15);
- int T = (sim->get_state(sim) == ARMV4_5_STATE_THUMB);
+ int T = (sim->get_state(sim) == ARM_STATE_THUMB);
sim->set_reg_mode(sim, 14, old_pc + 4 + T);
- if (target & 0x1)
+ if (target_address & 0x1)
{
- sim->set_state(sim, ARMV4_5_STATE_THUMB);
+ sim->set_state(sim, ARM_STATE_THUMB);
}
else
{
- sim->set_state(sim, ARMV4_5_STATE_ARM);
+ sim->set_state(sim, ARM_STATE_ARM);
}
- sim->set_reg(sim, 15, target & 0xfffffffe);
+ sim->set_reg(sim, 15, target_address & 0xfffffffe);
}
return ERROR_OK;
if (instruction.info.data_proc.Rd == 15) {
sim->set_reg_mode(sim, 15, Rd & ~1);
if (Rd & 1)
- sim->set_state(sim, ARMV4_5_STATE_THUMB);
+ sim->set_state(sim, ARM_STATE_THUMB);
else
- sim->set_state(sim, ARMV4_5_STATE_ARM);
+ sim->set_state(sim, ARM_STATE_ARM);
return ERROR_OK;
}
sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd);
/* load register instructions */
else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
{
- uint32_t load_address = 0, modified_address = 0, load_value;
+ uint32_t load_address = 0, modified_address = 0, load_value = 0;
uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store.Rn);
/* adjust Rn in case the PC is being read */
if (instruction.info.load_store.Rd == 15) {
sim->set_reg_mode(sim, 15, load_value & ~1);
if (load_value & 1)
- sim->set_state(sim, ARMV4_5_STATE_THUMB);
+ sim->set_state(sim, ARM_STATE_THUMB);
else
- sim->set_state(sim, ARMV4_5_STATE_ARM);
+ sim->set_state(sim, ARM_STATE_ARM);
return ERROR_OK;
}
sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value);
}
else
{
- enum armv4_5_mode mode = sim->get_mode(sim);
int update_cpsr = 0;
if (instruction.info.load_store_multiple.S)
{
if (instruction.info.load_store_multiple.register_list & 0x8000)
update_cpsr = 1;
- else
- mode = ARMV4_5_MODE_USR;
}
for (i = 0; i < 16; i++)
uint32_t val = load_values[i];
sim->set_reg_mode(sim, i, val & ~1);
if (val & 1)
- sim->set_state(sim, ARMV4_5_STATE_THUMB);
+ sim->set_state(sim, ARM_STATE_THUMB);
else
- sim->set_state(sim, ARMV4_5_STATE_ARM);
+ sim->set_state(sim, ARM_STATE_ARM);
} else {
sim->set_reg_mode(sim, i, load_values[i]);
}
uint32_t Rn = sim->get_reg_mode(sim,
instruction.info.load_store_multiple.Rn);
int bits_set = 0;
- enum armv4_5_mode mode = sim->get_mode(sim);
for (i = 0; i < 16; i++)
{
bits_set++;
}
- if (instruction.info.load_store_multiple.S)
- {
- mode = ARMV4_5_MODE_USR;
- }
-
switch (instruction.info.load_store_multiple.addressing_mode)
{
case 0: /* Increment after */
static uint32_t armv4_5_get_reg(struct arm_sim_interface *sim, int reg)
{
- struct arm *armv4_5 = (struct arm *)sim->user_data;
+ struct arm *arm = (struct arm *)sim->user_data;
- return buf_get_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32);
+ return buf_get_u32(arm->core_cache->reg_list[reg].value, 0, 32);
}
static void armv4_5_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
{
- struct arm *armv4_5 = (struct arm *)sim->user_data;
+ struct arm *arm = (struct arm *)sim->user_data;
- buf_set_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32, value);
+ buf_set_u32(arm->core_cache->reg_list[reg].value, 0, 32, value);
}
static uint32_t armv4_5_get_reg_mode(struct arm_sim_interface *sim, int reg)
{
- struct arm *armv4_5 = (struct arm *)sim->user_data;
+ struct arm *arm = (struct arm *)sim->user_data;
- return buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, reg).value, 0, 32);
+ return buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
+ arm->core_mode, reg).value, 0, 32);
}
static void armv4_5_set_reg_mode(struct arm_sim_interface *sim, int reg, uint32_t value)
{
- struct arm *armv4_5 = (struct arm *)sim->user_data;
+ struct arm *arm = (struct arm *)sim->user_data;
- buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, reg).value, 0, 32, value);
+ buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
+ arm->core_mode, reg).value, 0, 32, value);
}
static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
{
- struct arm *armv4_5 = (struct arm *)sim->user_data;
+ struct arm *arm = (struct arm *)sim->user_data;
- return buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, pos, bits);
+ return buf_get_u32(arm->cpsr->value, pos, bits);
}
-static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
+static enum arm_state armv4_5_get_state(struct arm_sim_interface *sim)
{
- struct arm *armv4_5 = (struct arm *)sim->user_data;
+ struct arm *arm = (struct arm *)sim->user_data;
- return armv4_5->core_state;
+ return arm->core_state;
}
-static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
+static void armv4_5_set_state(struct arm_sim_interface *sim, enum arm_state mode)
{
- struct arm *armv4_5 = (struct arm *)sim->user_data;
+ struct arm *arm = (struct arm *)sim->user_data;
- armv4_5->core_state = mode;
+ arm->core_state = mode;
}
-static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim)
+static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim)
{
- struct arm *armv4_5 = (struct arm *)sim->user_data;
+ struct arm *arm = (struct arm *)sim->user_data;
- return armv4_5->core_mode;
+ return arm->core_mode;
}
int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
{
- struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+ struct arm *arm = target_to_arm(target);
struct arm_sim_interface sim;
- sim.user_data = armv4_5;
+ sim.user_data = arm;
sim.get_reg = &armv4_5_get_reg;
sim.set_reg = &armv4_5_set_reg;
sim.get_reg_mode = &armv4_5_get_reg_mode;
projects / fw / openocd / blobdiff