u32 arm_shift(u8 shift, u32 Rm, u32 shift_amount, u8 *carry)
{
- u32 return_value;
+ u32 return_value = 0;
shift_amount &= 0xff;
if (shift == 0x0) /* LSL */
}
else
{
- ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
+ LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
return_value = 0xffffffff;
}
}
- ERROR("BUG: should never get here");
+ LOG_ERROR("BUG: should never get here");
return 0;
}
else
{
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rd).value, 0, 32, Rd);
- WARNING("no updating of flags yet");
+ LOG_WARNING("no updating of flags yet");
if (instruction.info.data_proc.Rd == 15)
return ERROR_OK;
}
else
{
- WARNING("no updating of flags yet");
+ LOG_WARNING("no updating of flags yet");
}
}
/* load register instructions */
else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
{
- u32 load_address, modified_address, load_value;
+ u32 load_address = 0, modified_address = 0, load_value;
u32 Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32);
/* adjust Rn in case the PC is being read */
}
else
{
- ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
+ LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
}
if (instruction.info.load_store.index_mode == 0)