#include "config.h"
#endif
-#include "target.h"
#include "armv4_5.h"
#include "arm_disassembler.h"
#include "arm_simulator.h"
#include "log.h"
#include "binarybuffer.h"
-#include <string.h>
-u32 arm_shift(u8 shift, u32 Rm, u32 shift_amount, u8 *carry)
+u32 arm_shift(uint8_t shift, u32 Rm, u32 shift_amount, uint8_t *carry)
{
u32 return_value = 0;
shift_amount &= 0xff;
return return_value;
}
-u32 arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_shifter_operand shifter_operand, u8 *shifter_carry_out)
+u32 arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_shifter_operand shifter_operand, uint8_t *shifter_carry_out)
{
u32 return_value;
int instruction_size;
return 0;
}
-int thumb_pass_branch_condition(u32 cpsr, u16 opcode)
+int thumb_pass_branch_condition(u32 cpsr, uint16_t opcode)
{
return pass_condition(cpsr, (opcode & 0x0f00) << 20);
}
}
else
{
- u16 opcode;
+ uint16_t opcode;
if((retval = target_read_u16(target, current_pc, &opcode)) != ERROR_OK)
{
|| ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN)))
{
u32 Rd, Rn, shifter_operand;
- u8 C = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
- u8 carry_out;
+ uint8_t C = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
+ uint8_t carry_out;
Rd = 0x0;
- Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rn).value, 0, 32);
+ /* ARM_MOV and ARM_MVN does not use Rn */
+ if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN))
+ Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rn).value, 0, 32);
+ else
+ Rn = 0;
+
shifter_operand = arm_shifter_operand(armv4_5, instruction.info.data_proc.variant, instruction.info.data_proc.shifter_operand, &carry_out);
/* adjust Rn in case the PC is being read */
Rd = shifter_operand;
else if (instruction.type == ARM_MVN)
Rd = ~shifter_operand;
+ else
+ LOG_WARNING("unhandled instruction type");
if (dry_run_pc)
{
{
u32 offset;
u32 Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.offset.reg.Rm).value, 0, 32);
- u8 shift = instruction.info.load_store.offset.reg.shift;
- u8 shift_imm = instruction.info.load_store.offset.reg.shift_imm;
- u8 carry = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
+ uint8_t shift = instruction.info.load_store.offset.reg.shift;
+ uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm;
+ uint8_t carry = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
offset = arm_shift(shift, Rm, shift_imm, &carry);