arm_adi_v5: mem_ap_write error propagation

[fw/openocd] / src / target / arm_opcodes.h

diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h
index b3b51433a8d55bbc311ebdcd43328a923250432c..b77721e6f9314d3258c1c47236889006466630ec 100644 (file)
--- a/src/target/arm_opcodes.h
+++ b/src/target/arm_opcodes.h
@@ -2,6 +2,9 @@
  * Copyright (C) 2005 by Dominic Rath
  * Dominic.Rath@gmx.de
  *
+ * Copyright (C) 2006 by Magnus Lundin
+ * lundin@mlu.mine.nu
+ *
  * Copyright (C) 2008 by Spencer Oliver
  * spen@spen-soft.co.uk
  *
@@ -26,6 +29,11 @@
 #ifndef __ARM_OPCODES_H
 #define __ARM_OPCODES_H
 
+/**
+ * @file
+ * Macros used to generate various ARM or Thumb opcodes.
+ */
+
 /* ARM mode instructions */
 
 /* Store multiple increment after
@@ -145,9 +153,13 @@
 
 /* Thumb mode instructions
  *
- * FIXME there must be some reason all these opcodes are 32-bits
- * not 16-bits ... this should get either an explanatory comment,
- * or be changed not to duplicate the opcode.
+ * NOTE: these 16-bit opcodes fill both halves of a word with the same
+ * value.  The reason for this is that when we need to execute Thumb
+ * opcodes on ARM7/ARM9 cores (to switch to ARM state on debug entry),
+ * we must shift 32 bits to the bus using scan chain 1 ... if we write
+ * both halves, we don't need to track which half matters.  On ARMv6 and
+ * ARMv7 we don't execute Thumb instructions in debug mode; the ITR
+ * register does not accept Thumb (or Thumb2) opcodes.
  */
 
 /* Store register (Thumb mode)