+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/*
* Copyright (C) 2009 by David Brownell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef OPENOCD_TARGET_ARM_DPM_H
uint64_t didr;
/** Invoke before a series of instruction operations */
- int (*prepare)(struct arm_dpm *);
+ int (*prepare)(struct arm_dpm *dpm);
/** Invoke after a series of instruction operations */
- int (*finish)(struct arm_dpm *);
+ int (*finish)(struct arm_dpm *dpm);
/** Runs one instruction. */
- int (*instr_execute)(struct arm_dpm *, uint32_t opcode);
+ int (*instr_execute)(struct arm_dpm *dpm, uint32_t opcode);
/* WRITE TO CPU */
/** Runs one instruction, writing data to DCC before execution. */
- int (*instr_write_data_dcc)(struct arm_dpm *,
+ int (*instr_write_data_dcc)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t data);
- int (*instr_write_data_dcc_64)(struct arm_dpm *,
+ int (*instr_write_data_dcc_64)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t data);
/** Runs one instruction, writing data to R0 before execution. */
- int (*instr_write_data_r0)(struct arm_dpm *,
+ int (*instr_write_data_r0)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t data);
/** Runs one instruction, writing data to R0 before execution. */
- int (*instr_write_data_r0_64)(struct arm_dpm *,
+ int (*instr_write_data_r0_64)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t data);
/** Optional core-specific operation invoked after CPSR writes. */
/* READ FROM CPU */
/** Runs one instruction, reading data from dcc after execution. */
- int (*instr_read_data_dcc)(struct arm_dpm *,
+ int (*instr_read_data_dcc)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t *data);
- int (*instr_read_data_dcc_64)(struct arm_dpm *,
+ int (*instr_read_data_dcc_64)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t *data);
/** Runs one instruction, reading data from r0 after execution. */
- int (*instr_read_data_r0)(struct arm_dpm *,
+ int (*instr_read_data_r0)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t *data);
- int (*instr_read_data_r0_64)(struct arm_dpm *,
+ int (*instr_read_data_r0_64)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t *data);
struct reg *(*arm_reg_current)(struct arm *arm,
* must currently be disabled. Indices 0..15 are used for
* breakpoints; indices 16..31 are for watchpoints.
*/
- int (*bpwp_enable)(struct arm_dpm *, unsigned index_value,
+ int (*bpwp_enable)(struct arm_dpm *dpm, unsigned index_value,
uint32_t addr, uint32_t control);
/**
* hardware control registers. Indices are the same ones
* accepted by bpwp_enable().
*/
- int (*bpwp_disable)(struct arm_dpm *, unsigned index_value);
+ int (*bpwp_disable)(struct arm_dpm *dpm, unsigned index_value);
/* The breakpoint and watchpoint arrays are private to the
* DPM infrastructure. There are nbp indices in the dbp
struct dpm_bp *dbp;
struct dpm_wp *dwp;
- /** Address of the instruction which triggered a watchpoint. */
- target_addr_t wp_pc;
+ /**
+ * Target dependent watchpoint address.
+ * Either the address of the instruction which triggered a watchpoint
+ * or the memory address whose access triggered a watchpoint.
+ */
+ target_addr_t wp_addr;
/** Recent value of DSCR. */
uint32_t dscr;
int arm_dpm_initialize(struct arm_dpm *dpm);
int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum);
-int arm_dpm_read_current_registers(struct arm_dpm *);
+int arm_dpm_read_current_registers(struct arm_dpm *dpm);
int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
-int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
+int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp);
-void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
+void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t wfar);
/* DSCR bits; see ARMv7a arch spec section C10.3.1.
* Not all v7 bits are valid in v6.
/* OSLSR (OS Lock Status Register) bits */
#define OSLSR_OSLM0 (1 << 0)
#define OSLSR_OSLK (1 << 1)
-#define OSLSR_nTT (1 << 2)
+#define OSLSR_NTT (1 << 2)
#define OSLSR_OSLM1 (1 << 3)
#define OSLSR_OSLM (OSLSR_OSLM0|OSLSR_OSLM1)