target/aarch64: a64 disassembler

[fw/openocd] / src / target / arm_dpm.h

diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index bbcae78535dc3fcaaf315d94c0bdb759fbcf5a13..82707822b1f90cf576533568305ebf98ba1d2584 100644 (file)
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -59,37 +59,56 @@ struct arm_dpm {
        struct arm *arm;
 
        /** Cache of DIDR */
-       uint32_t didr;
+       uint64_t didr;
 
        /** Invoke before a series of instruction operations */
-       int (*prepare)(struct arm_dpm *);
+       int (*prepare)(struct arm_dpm *dpm);
 
        /** Invoke after a series of instruction operations */
-       int (*finish)(struct arm_dpm *);
+       int (*finish)(struct arm_dpm *dpm);
+
+       /** Runs one instruction. */
+       int (*instr_execute)(struct arm_dpm *dpm, uint32_t opcode);
 
        /* WRITE TO CPU */
 
        /** Runs one instruction, writing data to DCC before execution. */
-       int (*instr_write_data_dcc)(struct arm_dpm *,
+       int (*instr_write_data_dcc)(struct arm_dpm *dpm,
                        uint32_t opcode, uint32_t data);
 
+       int (*instr_write_data_dcc_64)(struct arm_dpm *dpm,
+                       uint32_t opcode, uint64_t data);
+
        /** Runs one instruction, writing data to R0 before execution. */
-       int (*instr_write_data_r0)(struct arm_dpm *,
+       int (*instr_write_data_r0)(struct arm_dpm *dpm,
                        uint32_t opcode, uint32_t data);
 
+       /** Runs one instruction, writing data to R0 before execution. */
+       int (*instr_write_data_r0_64)(struct arm_dpm *dpm,
+                       uint32_t opcode, uint64_t data);
+
        /** Optional core-specific operation invoked after CPSR writes. */
        int (*instr_cpsr_sync)(struct arm_dpm *dpm);
 
        /* READ FROM CPU */
 
        /** Runs one instruction, reading data from dcc after execution. */
-       int (*instr_read_data_dcc)(struct arm_dpm *,
+       int (*instr_read_data_dcc)(struct arm_dpm *dpm,
                        uint32_t opcode, uint32_t *data);
 
+       int (*instr_read_data_dcc_64)(struct arm_dpm *dpm,
+                       uint32_t opcode, uint64_t *data);
+
        /** Runs one instruction, reading data from r0 after execution. */
-       int (*instr_read_data_r0)(struct arm_dpm *,
+       int (*instr_read_data_r0)(struct arm_dpm *dpm,
                        uint32_t opcode, uint32_t *data);
 
+       int (*instr_read_data_r0_64)(struct arm_dpm *dpm,
+                       uint32_t opcode, uint64_t *data);
+
+       struct reg *(*arm_reg_current)(struct arm *arm,
+                       unsigned regnum);
+
        /* BREAKPOINT/WATCHPOINT SUPPORT */
 
        /**
@@ -98,7 +117,7 @@ struct arm_dpm {
         * must currently be disabled.  Indices 0..15 are used for
         * breakpoints; indices 16..31 are for watchpoints.
         */
-       int (*bpwp_enable)(struct arm_dpm *, unsigned index_value,
+       int (*bpwp_enable)(struct arm_dpm *dpm, unsigned index_value,
                        uint32_t addr, uint32_t control);
 
        /**
@@ -106,7 +125,7 @@ struct arm_dpm {
         * hardware control registers.  Indices are the same ones
         * accepted by bpwp_enable().
         */
-       int (*bpwp_disable)(struct arm_dpm *, unsigned index_value);
+       int (*bpwp_disable)(struct arm_dpm *dpm, unsigned index_value);
 
        /* The breakpoint and watchpoint arrays are private to the
         * DPM infrastructure.  There are nbp indices in the dbp
@@ -119,24 +138,27 @@ struct arm_dpm {
        struct dpm_wp *dwp;
 
        /** Address of the instruction which triggered a watchpoint. */
-       uint32_t wp_pc;
+       target_addr_t wp_pc;
 
        /** Recent value of DSCR. */
        uint32_t dscr;
 
+       /** Recent exception level on armv8 */
+       unsigned int last_el;
+
        /* FIXME -- read/write DCSR methods and symbols */
 };
 
 int arm_dpm_setup(struct arm_dpm *dpm);
 int arm_dpm_initialize(struct arm_dpm *dpm);
 
-int arm_dpm_read_current_registers(struct arm_dpm *);
-int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
-
+int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum);
+int arm_dpm_read_current_registers(struct arm_dpm *dpm);
+int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
 
-int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
+int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp);
 
-void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
+void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t wfar);
 
 /* DSCR bits; see ARMv7a arch spec section C10.3.1.
  * Not all v7 bits are valid in v6.
@@ -166,21 +188,21 @@ void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
 #define DSCR_DTR_TX_FULL            (0x1 << 29)
 #define DSCR_DTR_RX_FULL            (0x1 << 30) /* bit 31 is reserved */
 
-#define DSCR_ENTRY(dscr)            (((dscr) >> 2) & 0xf)
-#define DSCR_RUN_MODE(dscr)         ((dscr) & (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED))
+#define DSCR_ENTRY(dscr)            ((dscr) & 0x3f)
+#define DSCR_RUN_MODE(dscr)         ((dscr) & 0x03)
 
 
 /* Methods of entry into debug mode */
-#define DSCR_ENTRY_HALT_REQ           (0x0 << 2)
-#define DSCR_ENTRY_BREAKPOINT         (0x1 << 2)
-#define DSCR_ENTRY_IMPRECISE_WATCHPT  (0x2 << 2)
-#define DSCR_ENTRY_BKPT_INSTR         (0x3 << 2)
-#define DSCR_ENTRY_EXT_DBG_REQ        (0x4 << 2)
-#define DSCR_ENTRY_VECT_CATCH         (0x5 << 2)
-#define DSCR_ENTRY_D_SIDE_ABORT       (0x6 << 2)  /* v6 only */
-#define DSCR_ENTRY_I_SIDE_ABORT       (0x7 << 2)  /* v6 only */
-#define DSCR_ENTRY_OS_UNLOCK          (0x8 << 2)
-#define DSCR_ENTRY_PRECISE_WATCHPT    (0xA << 2)
+#define DSCR_ENTRY_HALT_REQ           (0x03)
+#define DSCR_ENTRY_BREAKPOINT         (0x07)
+#define DSCR_ENTRY_IMPRECISE_WATCHPT  (0x0B)
+#define DSCR_ENTRY_BKPT_INSTR         (0x0F)
+#define DSCR_ENTRY_EXT_DBG_REQ        (0x13)
+#define DSCR_ENTRY_VECT_CATCH         (0x17)
+#define DSCR_ENTRY_D_SIDE_ABORT       (0x1B)  /* v6 only */
+#define DSCR_ENTRY_I_SIDE_ABORT       (0x1F)  /* v6 only */
+#define DSCR_ENTRY_OS_UNLOCK          (0x23)
+#define DSCR_ENTRY_PRECISE_WATCHPT    (0x2B)
 
 /* DTR modes */
 #define DSCR_EXT_DCC_NON_BLOCKING     (0x0 << 20)