* registers are compatible.
*/
-struct dpm_bp {
- struct breakpoint *bp;
- /* bp->address == breakpoint value register
- * control == breakpoint control register
- */
+struct dpm_bpwp {
+ unsigned number;
+ uint32_t address;
uint32_t control;
/* true if hardware state needs flushing */
bool dirty;
};
+struct dpm_bp {
+ struct breakpoint *bp;
+ struct dpm_bpwp bpwp;
+};
+
struct dpm_wp {
struct watchpoint *wp;
- /* wp->address == watchpoint value register
- * control == watchpoint control register
- */
- uint32_t control;
- /* true if hardware state needs flushing */
- bool dirty;
+ struct dpm_bpwp bpwp;
};
/**
* must currently be disabled. Indices 0..15 are used for
* breakpoints; indices 16..31 are for watchpoints.
*/
- int (*bpwp_enable)(struct arm_dpm *, unsigned index,
+ int (*bpwp_enable)(struct arm_dpm *, unsigned index_value,
uint32_t addr, uint32_t control);
/**
* hardware control registers. Indices are the same ones
* accepted by bpwp_enable().
*/
- int (*bpwp_disable)(struct arm_dpm *, unsigned index);
+ int (*bpwp_disable)(struct arm_dpm *, unsigned index_value);
/* The breakpoint and watchpoint arrays are private to the
* DPM infrastructure. There are nbp indices in the dbp
/** Recent value of DSCR. */
uint32_t dscr;
- // FIXME -- read/write DCSR methods and symbols
+ /* FIXME -- read/write DCSR methods and symbols */
};
int arm_dpm_setup(struct arm_dpm *dpm);
int arm_dpm_initialize(struct arm_dpm *dpm);
int arm_dpm_read_current_registers(struct arm_dpm *);
+int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
+
+
int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
#define DSCR_CORE_HALTED (1 << 0)
#define DSCR_CORE_RESTARTED (1 << 1)
#define DSCR_INT_DIS (1 << 11)
-#define DSCR_ITR_EN (1 << 13)
+#define DSCR_ITR_EN (1 << 13)
#define DSCR_HALT_DBG_MODE (1 << 14)
#define DSCR_MON_DBG_MODE (1 << 15)
#define DSCR_INSTR_COMP (1 << 24)
#define DSCR_DTR_TX_FULL (1 << 29)
#define DSCR_DTR_RX_FULL (1 << 30)
-#define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
+#define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
+#define DSCR_RUN_MODE(dscr) ((dscr) & (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED))
+
+/* DRCR (debug run control register) bits */
+#define DRCR_HALT (1 << 0)
+#define DRCR_RESTART (1 << 1)
+#define DRCR_CLEAR_EXCEPTIONS (1 << 2)
void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);