TARGET: review handle_load_image_command()

[fw/openocd] / src / target / arm_dpm.h

diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index 11213a36c7766641570a949e0f5ae13d8e1d6767..5d75ed4121f5730bada76e060a590b8d821eb658 100644 (file)
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -31,24 +31,22 @@
  * registers are compatible.
  */
 
-struct dpm_bp {
-       struct breakpoint *bp;
-       /* bp->address == breakpoint value register
-        * control == breakpoint control register
-        */
+struct dpm_bpwp {
+       unsigned number;
+       uint32_t address;
        uint32_t control;
        /* true if hardware state needs flushing */
        bool dirty;
 };
 
+struct dpm_bp {
+       struct breakpoint *bp;
+       struct dpm_bpwp bpwp;
+};
+
 struct dpm_wp {
        struct watchpoint *wp;
-       /* wp->address == watchpoint value register
-        * control == watchpoint control register
-        */
-       uint32_t control;
-       /* true if hardware state needs flushing */
-       bool dirty;
+       struct dpm_bpwp bpwp;
 };
 
 /**
@@ -125,6 +123,9 @@ struct arm_dpm {
        /** Address of the instruction which triggered a watchpoint. */
        uint32_t wp_pc;
 
+       /** Recent value of DSCR. */
+       uint32_t dscr;
+
        // FIXME -- read/write DCSR methods and symbols
 };
 
@@ -151,4 +152,6 @@ void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
 
 #define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
 
+void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
+
 #endif /* __ARM_DPM_H */