#include "config.h"
#endif
-#include "armv4_5.h" /* REVISIT to become arm.h */
+#include "arm.h"
#include "arm_dpm.h"
#include <jtag/jtag.h>
#include "register.h"
#include "breakpoints.h"
#include "target_type.h"
+#include "arm_opcodes.h"
/**
/* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
* Routines *must* restore the original mode before returning!!
*/
-static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode)
+static int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
{
int retval;
uint32_t cpsr;
retval = dpm->bpwp_disable(dpm, 16 + i);
else
retval = dpm->bpwp_enable(dpm, 16 + i,
- wp->address, dwp->control);
+ wp->address & ~3, dwp->control);
if (retval != ERROR_OK)
LOG_ERROR("%s: can't %s HW watchpoint %d",
* actually find anything to do...
*/
do {
- enum armv4_5_mode mode = ARM_MODE_ANY;
+ enum arm_mode mode = ARM_MODE_ANY;
did_write = false;
/* may need to pick and set a mode */
if (!did_write) {
- enum armv4_5_mode tmode;
+ enum arm_mode tmode;
did_write = true;
mode = tmode = r->mode;
* Caller already filtered out SPSR access; mode is never MODE_SYS
* or MODE_ANY.
*/
-static enum armv4_5_mode dpm_mapmode(struct arm *arm,
- unsigned num, enum armv4_5_mode mode)
+static enum arm_mode dpm_mapmode(struct arm *arm,
+ unsigned num, enum arm_mode mode)
{
- enum armv4_5_mode amode = arm->core_mode;
+ enum arm_mode amode = arm->core_mode;
/* don't switch if the mode is already correct */
if (amode == ARM_MODE_SYS)
*/
static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
- int regnum, enum armv4_5_mode mode)
+ int regnum, enum arm_mode mode)
{
struct arm_dpm *dpm = target_to_arm(target)->dpm;
int retval;
}
static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
- int regnum, enum armv4_5_mode mode, uint32_t value)
+ int regnum, enum arm_mode mode, uint32_t value)
{
struct arm_dpm *dpm = target_to_arm(target)->dpm;
int retval;
goto done;
do {
- enum armv4_5_mode mode = ARM_MODE_ANY;
+ enum arm_mode mode = ARM_MODE_ANY;
did_read = false;
arm->read_core_reg = arm_dpm_read_core_reg;
arm->write_core_reg = arm_dpm_write_core_reg;
- cache = armv4_5_build_reg_cache(target, arm);
+ cache = arm_build_reg_cache(target, arm);
if (!cache)
return ERROR_FAIL;