+// SPDX-License-Identifier: GPL-2.0-or-later
+
/*
* Copyright (C) 2009 by David Brownell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifdef HAVE_CONFIG_H
/* Read coprocessor */
static int dpm_mrc(struct target *target, int cpnum,
- uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
+ uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
uint32_t *value)
{
struct arm *arm = target_to_arm(target);
return retval;
LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
- (int) op1, (int) CRn,
- (int) CRm, (int) op2);
+ (int) op1, (int) crn,
+ (int) crm, (int) op2);
/* read coprocessor register into R0; return via DCC */
retval = dpm->instr_read_data_r0(dpm,
- ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
+ ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
value);
/* (void) */ dpm->finish(dpm);
}
static int dpm_mcr(struct target *target, int cpnum,
- uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
+ uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
uint32_t value)
{
struct arm *arm = target_to_arm(target);
return retval;
LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
- (int) op1, (int) CRn,
- (int) CRm, (int) op2);
+ (int) op1, (int) crn,
+ (int) crm, (int) op2);
/* read DCC into r0; then write coprocessor register from R0 */
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
+ ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
value);
/* (void) */ dpm->finish(dpm);
* or running debugger code.
*/
static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
- struct dpm_bpwp *xp, int *set_p)
+ struct dpm_bpwp *xp, bool *set_p)
{
int retval = ERROR_OK;
bool disable;
struct breakpoint *bp = dbp->bp;
retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
- bp ? &bp->set : NULL);
+ bp ? &bp->is_set : NULL);
if (retval != ERROR_OK)
goto done;
}
struct watchpoint *wp = dwp->wp;
retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
- wp ? &wp->set : NULL);
+ wp ? &wp->is_set : NULL);
if (retval != ERROR_OK)
goto done;
}
continue;
if (arm->cpsr == cache->reg_list + i)
continue;
- if (!cache->reg_list[i].dirty)
+ if (!cache->reg_list[i].exist || !cache->reg_list[i].dirty)
continue;
r = cache->reg_list[i].arch_info;
for (unsigned i = 0; i < cache->num_regs; i++) {
struct arm_reg *r;
- if (cache->reg_list[i].valid)
+ if (!cache->reg_list[i].exist || cache->reg_list[i].valid)
continue;
r = cache->reg_list[i].arch_info;
/* ?? */
break;
}
- dpm->wp_pc = addr;
+ dpm->wp_addr = addr;
}
/*----------------------------------------------------------------------*/
arm->read_core_reg = arm_dpm_read_core_reg;
arm->write_core_reg = arm_dpm_write_core_reg;
- if (arm->core_cache == NULL) {
+ if (!arm->core_cache) {
cache = arm_build_reg_cache(target, arm);
if (!cache)
return ERROR_FAIL;
target->type->remove_breakpoint = dpm_remove_breakpoint;
}
- /* watchpoint setup */
- target->type->add_watchpoint = dpm_add_watchpoint;
- target->type->remove_watchpoint = dpm_remove_watchpoint;
+ /* watchpoint setup -- optional until it works everywhere */
+ if (!target->type->add_watchpoint) {
+ target->type->add_watchpoint = dpm_add_watchpoint;
+ target->type->remove_watchpoint = dpm_remove_watchpoint;
+ }
/* FIXME add vector catch support */