target/armv7m: rework Cortex-M register handling part 1

[fw/openocd] / src / target / arm_disassembler.h

diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index a3d16f5fa7741cadee34eae11d4d92edfa57577c..beecb3f30ffd8ef8fdd21becc59fdf827e75a479 100644 (file)
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -13,18 +13,14 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
-#ifndef ARM_DISASSEMBLER_H
-#define ARM_DISASSEMBLER_H
 
-#include "types.h"
+#ifndef OPENOCD_TARGET_ARM_DISASSEMBLER_H
+#define OPENOCD_TARGET_ARM_DISASSEMBLER_H
 
-enum arm_instruction_type
-{
-       ARM_UNKNOWN_INSTUCTION,
+enum arm_instruction_type {
+       ARM_UNKNOWN_INSTRUCTION,
 
        /* Branch instructions */
        ARM_B,
@@ -86,9 +82,14 @@ enum arm_instruction_type
        /* Miscellaneous instructions */
        ARM_CLZ,
 
+       /* Exception return instructions */
+       ARM_ERET,
+
        /* Exception generating instructions */
        ARM_BKPT,
        ARM_SWI,
+       ARM_HVC,
+       ARM_SMC,
 
        /* Coprocessor instructions */
        ARM_CDP,
@@ -105,6 +106,8 @@ enum arm_instruction_type
        ARM_MCRR,
        ARM_MRRC,
        ARM_PLD,
+       ARM_DSB,
+       ARM_ISB,
        ARM_QADD,
        ARM_QDADD,
        ARM_QSUB,
@@ -120,14 +123,12 @@ enum arm_instruction_type
        ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
 };
 
-struct arm_b_bl_bx_blx_instr
-{
+struct arm_b_bl_bx_blx_instr {
        int reg_operand;
        uint32_t target_address;
 };
 
-union arm_shifter_operand
-{
+union arm_shifter_operand {
        struct {
                uint32_t immediate;
        } immediate;
@@ -143,8 +144,7 @@ union arm_shifter_operand
        } register_shift;
 };
 
-struct arm_data_proc_instr
-{
+struct arm_data_proc_instr {
        int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
        uint8_t S;
        uint8_t Rn;
@@ -152,15 +152,13 @@ struct arm_data_proc_instr
        union arm_shifter_operand shifter_operand;
 };
 
-struct arm_load_store_instr
-{
+struct arm_load_store_instr {
        uint8_t Rd;
        uint8_t Rn;
        uint8_t U;
        int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
        int offset_mode; /* 0: immediate, 1: (scaled) register */
-       union
-       {
+       union {
                uint32_t offset;
                struct {
                        uint8_t Rm;
@@ -170,8 +168,7 @@ struct arm_load_store_instr
        } offset;
 };
 
-struct arm_load_store_multiple_instr
-{
+struct arm_load_store_multiple_instr {
        uint8_t Rn;
        uint32_t register_list;
        uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
@@ -179,8 +176,7 @@ struct arm_load_store_multiple_instr
        uint8_t W;
 };
 
-struct arm_instruction
-{
+struct arm_instruction {
        enum arm_instruction_type type;
        char text[128];
        uint32_t opcode;
@@ -201,10 +197,12 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
                struct arm_instruction *instruction);
 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
                struct arm_instruction *instruction);
-int thumb2_opcode(target_t *target, uint32_t address,
-               struct arm_instruction *instruction);
 int arm_access_size(struct arm_instruction *instruction);
+#if HAVE_CAPSTONE
+int arm_disassemble(struct command_invocation *cmd, struct target *target,
+               target_addr_t address, size_t count, bool thumb_mode);
+#endif
 
 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
 
-#endif /* ARM_DISASSEMBLER_H */
+#endif /* OPENOCD_TARGET_ARM_DISASSEMBLER_H */