target/armv7m: rework Cortex-M register handling part 3

[fw/openocd] / src / target / arm_disassembler.h

diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index 22485602ed14486884eaad3a484c94ac7fc7048d..beecb3f30ffd8ef8fdd21becc59fdf827e75a479 100644 (file)
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -16,11 +16,11 @@
  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
-#ifndef ARM_DISASSEMBLER_H
-#define ARM_DISASSEMBLER_H
+#ifndef OPENOCD_TARGET_ARM_DISASSEMBLER_H
+#define OPENOCD_TARGET_ARM_DISASSEMBLER_H
 
 enum arm_instruction_type {
-       ARM_UNKNOWN_INSTUCTION,
+       ARM_UNKNOWN_INSTRUCTION,
 
        /* Branch instructions */
        ARM_B,
@@ -106,6 +106,8 @@ enum arm_instruction_type {
        ARM_MCRR,
        ARM_MRRC,
        ARM_PLD,
+       ARM_DSB,
+       ARM_ISB,
        ARM_QADD,
        ARM_QDADD,
        ARM_QSUB,
@@ -195,10 +197,12 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
                struct arm_instruction *instruction);
 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
                struct arm_instruction *instruction);
-int thumb2_opcode(struct target *target, uint32_t address,
-               struct arm_instruction *instruction);
 int arm_access_size(struct arm_instruction *instruction);
+#if HAVE_CAPSTONE
+int arm_disassemble(struct command_invocation *cmd, struct target *target,
+               target_addr_t address, size_t count, bool thumb_mode);
+#endif
 
 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
 
-#endif /* ARM_DISASSEMBLER_H */
+#endif /* OPENOCD_TARGET_ARM_DISASSEMBLER_H */