cortex_m: Fix single stepping will not return to debug mode sometimes

[fw/openocd] / src / target / arm_disassembler.h

diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index a8b9aba115938f45d59e7f1292d4432960b3c1f9..07564d6d8f216e288cb7ec7cf10541f074dc2ece 100644 (file)
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -17,13 +17,11 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+
 #ifndef ARM_DISASSEMBLER_H
 #define ARM_DISASSEMBLER_H
 
-#include "types.h"
-
-enum arm_instruction_type
-{
+enum arm_instruction_type {
        ARM_UNKNOWN_INSTUCTION,
 
        /* Branch instructions */
@@ -120,14 +118,12 @@ enum arm_instruction_type
        ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
 };
 
-typedef struct arm_b_bl_bx_blx_instr_s
-{
+struct arm_b_bl_bx_blx_instr {
        int reg_operand;
        uint32_t target_address;
-} arm_b_bl_bx_blx_instr_t;
+};
 
-union arm_shifter_operand
-{
+union arm_shifter_operand {
        struct {
                uint32_t immediate;
        } immediate;
@@ -143,24 +139,21 @@ union arm_shifter_operand
        } register_shift;
 };
 
-typedef struct arm_data_proc_instr_s
-{
+struct arm_data_proc_instr {
        int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
        uint8_t S;
        uint8_t Rn;
        uint8_t Rd;
        union arm_shifter_operand shifter_operand;
-} arm_data_proc_instr_t;
+};
 
-typedef struct arm_load_store_instr_s
-{
+struct arm_load_store_instr {
        uint8_t Rd;
        uint8_t Rn;
        uint8_t U;
        int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
        int offset_mode; /* 0: immediate, 1: (scaled) register */
-       union
-       {
+       union {
                uint32_t offset;
                struct {
                        uint8_t Rm;
@@ -168,35 +161,40 @@ typedef struct arm_load_store_instr_s
                        uint8_t shift_imm;
                } reg;
        } offset;
-} arm_load_store_instr_t;
+};
 
-typedef struct arm_load_store_multiple_instr_s
-{
+struct arm_load_store_multiple_instr {
        uint8_t Rn;
        uint32_t register_list;
        uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
        uint8_t S;
        uint8_t W;
-} arm_load_store_multiple_instr_t;
+};
 
-typedef struct arm_instruction_s
-{
+struct arm_instruction {
        enum arm_instruction_type type;
        char text[128];
        uint32_t opcode;
 
+       /* return value ... Thumb-2 sizes vary */
+       unsigned instruction_size;
+
        union {
-               arm_b_bl_bx_blx_instr_t b_bl_bx_blx;
-               arm_data_proc_instr_t data_proc;
-               arm_load_store_instr_t load_store;
-               arm_load_store_multiple_instr_t load_store_multiple;
+               struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
+               struct arm_data_proc_instr data_proc;
+               struct arm_load_store_instr load_store;
+               struct arm_load_store_multiple_instr load_store_multiple;
        } info;
 
-} arm_instruction_t;
+};
 
-extern int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *instruction);
-extern int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *instruction);
-extern int arm_access_size(arm_instruction_t *instruction);
+int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
+               struct arm_instruction *instruction);
+int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
+               struct arm_instruction *instruction);
+int thumb2_opcode(struct target *target, uint32_t address,
+               struct arm_instruction *instruction);
+int arm_access_size(struct arm_instruction *instruction);
 
 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])