}
else
{
+ /* REVISIT: if reg_imm == 0, display as "MOVS" */
instruction->type = ARM_ADD;
mnemonic = "ADDS";
}
break;
case 0x9:
instruction->type = ARM_RSB;
- mnemonic = "NEGS";
+ mnemonic = "RSBS";
instruction->info.data_proc.variant = 0 /*immediate*/;
instruction->info.data_proc.shifter_operand.immediate.immediate = 0;
instruction->info.data_proc.Rn = Rm;
if ((opcode & 0xf000) == 0xc000)
{ /* generic load/store multiple */
+ char *wback = "!";
+
if (L)
{
instruction->type = ARM_LDM;
mnemonic = "LDM";
+ if (opcode & (1 << Rn))
+ wback = "";
}
else
{
instruction->type = ARM_STM;
mnemonic = "STM";
}
- snprintf(ptr_name,7,"r%i!, ",Rn);
+ snprintf(ptr_name, sizeof ptr_name, "r%i%s, ", Rn, wback);
}
else
{ /* push/pop */
char *suffix;
/* added in ARMv6 */
- switch (opcode & 0x00c0) {
+ switch ((opcode >> 6) & 3) {
case 0:
suffix = "";
break;
mnemonic = "TST";
one = true;
suffix = "";
- suffix2 = ".W";
rd = rn;
} else {
instruction->type = ARM_AND;
case 10:
instruction->type = ARM_ADC;
mnemonic = "ADC";
+ suffix2 = ".W";
break;
case 11:
instruction->type = ARM_SBC;
bool add = false;
bool is_signed = false;
- immed = (opcode & 0x0ff) | ((opcode & 0x7000) >> 12);
- if (opcode & (1 << 27))
+ immed = (opcode & 0x0ff) | ((opcode & 0x7000) >> 4);
+ if (opcode & (1 << 26))
immed |= (1 << 11);
switch ((opcode >> 20) & 0x1f) {
add = true;
goto do_adr;
}
- mnemonic = "ADD.W";
+ mnemonic = "ADDW";
break;
case 4:
- mnemonic = "MOV.W";
- break;
+ immed |= (opcode >> 4) & 0xf000;
+ sprintf(cp, "MOVW\tr%d, #%d\t; %#3.3x", rd, immed, immed);
+ return ERROR_OK;
case 0x0a:
if (rn == 0xf)
goto do_adr;
- mnemonic = "SUB.W";
+ mnemonic = "SUBW";
break;
case 0x0c:
/* move constant to top 16 bits of register */
immed |= (opcode >> 10) & 0x1c;
sprintf(cp, "%sSAT\tr%d, #%d, r%d, %s #%d\t",
is_signed ? "S" : "U",
- rd, (int) (opcode & 0x1f) + 1, rn,
+ rd, (int) (opcode & 0x1f) + is_signed, rn,
(opcode & (1 << 21)) ? "ASR" : "LSL",
immed ? immed : 32);
return ERROR_OK;
sprintf(cp, "STR%s.W\tr%d, [r%d, r%d, LSL #%d]",
size, rt, rn, (int) opcode & 0x0f,
(int) (opcode >> 4) & 0x03);
+ return ERROR_OK;
imm12:
immed = opcode & 0x0fff;
switch (op) {
case 2:
- sprintf(cp, "STMB\tr%d%s, ", rn, t ? "!" : "");
+ sprintf(cp, "STM.W\tr%d%s, ", rn, t ? "!" : "");
break;
case 3:
if (rn == 13 && t)
- sprintf(cp, "POP\t");
+ sprintf(cp, "POP.W\t");
else
sprintf(cp, "LDM.W\tr%d%s, ", rn, t ? "!" : "");
break;
case 4:
if (rn == 13 && t)
- sprintf(cp, "PUSH\t");
+ sprintf(cp, "PUSH.W\t");
else
- sprintf(cp, "STM.W\tr%d%s, ", rn, t ? "!" : "");
+ sprintf(cp, "STMDB\tr%d%s, ", rn, t ? "!" : "");
break;
case 5:
- sprintf(cp, "LDMB\tr%d%s, ", rn, t ? "!" : "");
+ sprintf(cp, "LDMDB.W\tr%d%s, ", rn, t ? "!" : "");
break;
default:
return ERROR_INVALID_ARGUMENTS;
char *mnemonic;
char *suffix = "";
- immed |= (opcode >> 10) & 0x7;
- if (opcode & (1 << 21))
+ immed |= (opcode >> 10) & 0x1c;
+ if (opcode & (1 << 20))
suffix = "S";
switch (op) {
case 0:
if (rd == 0xf) {
- if (!(opcode & (1 << 21)))
+ if (!(opcode & (1 << 20)))
return ERROR_INVALID_ARGUMENTS;
instruction->type = ARM_TST;
mnemonic = "TST";
+ suffix = "";
goto two;
}
instruction->type = ARM_AND;
break;
default:
if (immed == 0) {
- sprintf(cp, "RRX%s.W\tr%d, r%d",
+ sprintf(cp, "RRX%s\tr%d, r%d",
suffix, rd,
(int) (opcode & 0xf));
return ERROR_OK;
break;
case 4:
if (rd == 0xf) {
- if (!(opcode & (1 << 21)))
+ if (!(opcode & (1 << 20)))
return ERROR_INVALID_ARGUMENTS;
instruction->type = ARM_TEQ;
mnemonic = "TEQ";
+ suffix = "";
goto two;
}
instruction->type = ARM_EOR;
break;
case 8:
if (rd == 0xf) {
- if (!(opcode & (1 << 21)))
+ if (!(opcode & (1 << 20)))
return ERROR_INVALID_ARGUMENTS;
instruction->type = ARM_CMN;
mnemonic = "CMN";
+ suffix = "";
goto two;
}
instruction->type = ARM_ADD;
return ERROR_INVALID_ARGUMENTS;
instruction->type = ARM_CMP;
mnemonic = "CMP";
+ suffix = "";
goto two;
}
instruction->type = ARM_SUB;
break;
case 1:
suffix = "LSR";
+ if (immed == 32)
+ immed = 0;
break;
case 2:
suffix = "ASR";
+ if (immed == 32)
+ immed = 0;
break;
case 3:
if (immed == 0) {
- strcpy(cp, "RRX");
+ strcpy(cp, ", RRX");
return ERROR_OK;
}
suffix = "ROR";
(int) (opcode >> 0) & 0xf);
} else if (opcode & (1 << 7)) {
- switch ((opcode >> 24) & 0xf) {
+ switch ((opcode >> 20) & 0xf) {
case 0:
case 1:
case 4:
(opcode & (1 << 24)) ? 'U' : 'S',
(opcode & (1 << 26)) ? 'B' : 'H',
(int) (opcode >> 8) & 0xf,
- (int) (opcode >> 16) & 0xf,
+ (int) (opcode >> 0) & 0xf,
suffix);
break;
case 8:
case 0xb:
if (opcode & (1 << 6))
return ERROR_INVALID_ARGUMENTS;
- if (~opcode & (0xff << 12))
+ if (((opcode >> 12) & 0xf) != 0xf)
return ERROR_INVALID_ARGUMENTS;
if (!(opcode & (1 << 20)))
return ERROR_INVALID_ARGUMENTS;
if (rn == 0xf) {
immed = opcode & 0x0fff;
- if (opcode & (1 << 23))
+ if ((opcode & (1 << 23)) == 0)
immed = -immed;
sprintf(cp, "LDR\tr%d, %#8.8" PRIx32,
(int) (opcode >> 12) & 0xf,
if (((opcode >> 8) & 0xf) == 0xc || (opcode & 0x0900) == 0x0900) {
char *p1 = "]", *p2 = "";
- if (!(opcode & 0x0600))
+ if (!(opcode & 0x0500))
return ERROR_INVALID_ARGUMENTS;
immed = opcode & 0x00ff;
int rt = (opcode >> 12) & 0xf;
int op2 = (opcode >> 6) & 0x3f;
unsigned immed;
- char *p1 = "]", *p2 = "";
+ char *p1 = "", *p2 = "]";
char *mnemonic;
switch ((opcode >> 23) & 0x3) {
case 0:
if ((rn & rt) == 0xf) {
-preload_immediate_t2:
+pld_literal:
immed = opcode & 0xfff;
-preload_immediate_t1:
- p1 = (opcode & (1 << 21)) ? "W" : "";
- sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x",
- p1, rn, immed, immed);
+ address = thumb_alignpc4(address);
+ if (opcode & (1 << 23))
+ address += immed;
+ else
+ address -= immed;
+ sprintf(cp, "PLD\tr%d, %#8.8" PRIx32,
+ rt, address);
return ERROR_OK;
}
if (rn == 0x0f && rt != 0x0f) {
if ((op2 & 0x3c) == 0x30) {
if (rt == 0x0f) {
immed = opcode & 0xff;
- goto preload_immediate_t1;
+ immed = -immed;
+preload_immediate:
+ p1 = (opcode & (1 << 21)) ? "W" : "";
+ sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x",
+ p1, rn, immed, immed);
+ return ERROR_OK;
}
mnemonic = "LDRB";
ldrxb_immediate_t3:
immed = opcode & 0xff;
- if (opcode & 0x200)
+ if (!(opcode & 0x200))
immed = -immed;
/* two indexed modes will write back rn */
}
break;
case 1:
- if (rt == 0xf)
- goto preload_immediate_t2;
+ if ((rn & rt) == 0xf)
+ goto pld_literal;
+ if (rt == 0xf) {
+ immed = opcode & 0xfff;
+ goto preload_immediate;
+ }
if (rn == 0x0f)
goto ldrb_literal;
mnemonic = "LDRB.W";
goto ldrxb_immediate_t2;
case 2:
if ((rn & rt) == 0xf) {
-pli_immediate:
immed = opcode & 0xfff;
address = thumb_alignpc4(address);
if (opcode & (1 << 23))
break;
if ((op2 & 0x3c) == 0x38) {
immed = opcode & 0xff;
- sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %2.2x",
+ sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %#2.2x",
rt, rn, immed, immed);
return ERROR_OK;
}
if (rt == 0xf) {
immed = opcode & 0xff;
immed = -immed; // pli
- sprintf(cp, "PLI\t[r%d, #-%d]\t; %2.2x",
- rn, immed, immed);
+ sprintf(cp, "PLI\t[r%d, #%d]\t; -%#2.2x",
+ rn, immed, -immed);
return ERROR_OK;
}
mnemonic = "LDRSB";
}
break;
case 3:
- if (rt == 0xf)
- goto pli_immediate;
+ if (rt == 0xf) {
+ immed = opcode & 0xfff;
+ sprintf(cp, "PLI\t[r%d, #%d]\t; %#3.3" PRIx32,
+ rn, immed, immed);
+ return ERROR_OK;
+ }
if (rn == 0xf)
goto ldrsb_literal;
immed = opcode & 0xfff;
return ERROR_INVALID_ARGUMENTS;
}
+static int t2ev_load_halfword(uint32_t opcode, uint32_t address,
+ arm_instruction_t *instruction, char *cp)
+{
+ int rn = (opcode >> 16) & 0xf;
+ int rt = (opcode >> 12) & 0xf;
+ int op2 = (opcode >> 6) & 0x3f;
+ char *sign = "";
+ unsigned immed;
+
+ if (rt == 0xf) {
+ sprintf(cp, "HINT (UNALLOCATED)");
+ return ERROR_OK;
+ }
+
+ if (opcode & (1 << 24))
+ sign = "S";
+
+ if ((opcode & (1 << 23)) == 0) {
+ if (rn == 0xf) {
+ldrh_literal:
+ immed = opcode & 0xfff;
+ address = thumb_alignpc4(address);
+ if (opcode & (1 << 23))
+ address += immed;
+ else
+ address -= immed;
+ sprintf(cp, "LDR%sH\tr%d, %#8.8" PRIx32,
+ sign, rt, address);
+ return ERROR_OK;
+ }
+ if (op2 == 0) {
+ int rm = opcode & 0xf;
+
+ immed = (opcode >> 4) & 0x3;
+ sprintf(cp, "LDR%sH.W\tr%d, [r%d, r%d, LSL #%d]",
+ sign, rt, rn, rm, immed);
+ return ERROR_OK;
+ }
+ if ((op2 & 0x3c) == 0x38) {
+ immed = opcode & 0xff;
+ sprintf(cp, "LDR%sHT\tr%d, [r%d, #%d]\t; %#2.2x",
+ sign, rt, rn, immed, immed);
+ return ERROR_OK;
+ }
+ if ((op2 & 0x3c) == 0x30 || (op2 & 0x24) == 0x24) {
+ char *p1 = "", *p2 = "]";
+
+ immed = opcode & 0xff;
+ if (!(opcode & 0x200))
+ immed = -immed;
+
+ /* two indexed modes will write back rn */
+ if (opcode & 0x100) {
+ if (opcode & 0x400) /* pre-indexed */
+ p2 = "]!";
+ else { /* post-indexed */
+ p1 = "]";
+ p2 = "";
+ }
+ }
+ sprintf(cp, "LDR%sH\tr%d, [r%d%s, #%d%s\t; %#8.8x",
+ sign, rt, rn, p1, immed, p2, immed);
+ return ERROR_OK;
+ }
+ } else {
+ if (rn == 0xf)
+ goto ldrh_literal;
+
+ immed = opcode & 0xfff;
+ sprintf(cp, "LDR%sH%s\tr%d, [r%d, #%d]\t; %#6.6x",
+ sign, *sign ? "" : ".W",
+ rt, rn, immed, immed);
+ return ERROR_OK;
+ }
+
+ return ERROR_INVALID_ARGUMENTS;
+}
+
/*
* REVISIT for Thumb2 instructions, instruction->type and friends aren't
* always set. That means eventual arm_simulate_step() support for Thumb2
else if ((opcode & 0x1f700000) == 0x18500000)
retval = t2ev_load_word(opcode, address, instruction, cp);
+ /* ARMv7-M: A5.3.8 Load halfword, unallocated memory hints */
+ else if ((opcode & 0x1e700000) == 0x18300000)
+ retval = t2ev_load_halfword(opcode, address, instruction, cp);
+
/* ARMv7-M: A5.3.9 Load byte, memory hints */
else if ((opcode & 0x1e700000) == 0x18100000)
retval = t2ev_load_byte_hints(opcode, address, instruction, cp);
else if ((opcode & 0x1e000000) == 0x0a000000)
retval = t2ev_data_shift(opcode, address, instruction, cp);
- /* ARMv7-M: A5.3.12 Data processing (register) */
+ /* ARMv7-M: A5.3.12 Data processing (register)
+ * and A5.3.13 Miscellaneous operations
+ */
else if ((opcode & 0x1f000000) == 0x1a000000)
retval = t2ev_data_reg(opcode, address, instruction, cp);
projects / fw / openocd / blobdiff