Fix "unused variable" warnings (errors) detected with GCC 4.7.0 - trivial fixes

[fw/openocd] / src / target / arm_disassembler.c

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 770c5e9c7a106c341eec250be21a29d72f047f83..36566c9932ec725a52814100e1fbfceb5429cdec 100644 (file)
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -50,6 +50,7 @@
  *       except as coprocessor 10/11 operations
  *     * Most ARM instructions through ARMv6 are decoded, but some
  *       of the post-ARMv4 opcodes may not be handled yet
+ *             CPS, SDIV, UDIV, LDREX*, STREX*, QASX, ...
  *     * NEON instructions are not understood (ARMv7-A)
  *
  *  - Thumb/Thumb2 decoding
@@ -299,7 +300,7 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
        else /* LDC or STC */
        {
                uint8_t CRd, Rn, offset;
-               uint8_t U, N;
+               uint8_t U;
                char *mnemonic;
                char addressing_mode[32];
 
@@ -320,7 +321,6 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
                }
 
                U = (opcode & 0x00800000) >> 23;
-               N = (opcode & 0x00400000) >> 22;
 
                /* addressing modes */
                if ((opcode & 0x01200000) == 0x01000000) /* offset */
@@ -1097,8 +1097,11 @@ static int evaluate_ldm_stm(uint32_t opcode,
                }
        }
 
-       snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i%s, {%s}%s",
-                        address, opcode, mnemonic, COND(opcode), addressing_mode,
+       snprintf(instruction->text, 128,
+                       "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
+                       "\t%s%s%s r%i%s, {%s}%s",
+                        address, opcode,
+                        mnemonic, addressing_mode, COND(opcode),
                         Rn, (W) ? "!" : "", reg_list, (S) ? "^" : "");
 
        return ERROR_OK;
@@ -2350,7 +2353,7 @@ static int evaluate_add_sp_pc_thumb(uint16_t opcode,
        uint8_t Rd = (opcode >> 8) & 0x7;
        uint8_t Rn;
        uint32_t SP = opcode & (1 << 11);
-       char *reg_name;
+       const char *reg_name;
 
        instruction->type = ARM_ADD;
 
@@ -3244,7 +3247,7 @@ static int t2ev_data_immed(uint32_t opcode, uint32_t address,
        case 0x0c:
                /* move constant to top 16 bits of register */
                immed |= (opcode >> 4) & 0xf000;
-               sprintf(cp, "MOVT\tr%d, #%d\t; %#4.4x", rn, immed, immed);
+               sprintf(cp, "MOVT\tr%d, #%d\t; %#4.4x", rd, immed, immed);
                return ERROR_OK;
        case 0x10:
        case 0x12: