* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
-#ifndef ARM_ADI_V5_H
-#define ARM_ADI_V5_H
+#ifndef OPENOCD_TARGET_ARM_ADI_V5_H
+#define OPENOCD_TARGET_ARM_ADI_V5_H
/**
* @file
* resources accessed through a MEM-AP.
*/
+#include <helper/list.h>
#include "arm_jtag.h"
+#include "helper/bits.h"
-/* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
- * is no longer JTAG-specific
- */
-#define JTAG_DP_DPACC 0xA
-#define JTAG_DP_APACC 0xB
+/* JEP106 ID for ARM */
+#define ARM_ID 0x23B
/* three-bit ACK values for SWD access (sent LSB first) */
#define SWD_ACK_OK 0x1
/* A[3:0] for DP registers; A[1:0] are always zero.
* - JTAG accesses all of these via JTAG_DP_DPACC, except for
* IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
- * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
+ * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
*/
-#define DP_IDCODE BANK_REG(0x0, 0x0) /* SWD: read */
-#define DP_ABORT BANK_REG(0x0, 0x0) /* SWD: write */
-#define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* r/w */
-#define DP_RESEND BANK_REG(0x0, 0x8) /* SWD: read */
-#define DP_SELECT BANK_REG(0x0, 0x8) /* JTAG: r/w; SWD: write */
-#define DP_RDBUFF BANK_REG(0x0, 0xC) /* read-only */
-#define DP_WCR BANK_REG(0x1, 0x4) /* SWD: r/w */
-
-#define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8))) /* 1..4 clocks */
-#define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */
+#define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
+#define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
+#define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
+#define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
+#define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
+#define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
+#define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
+#define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
+#define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
+#define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
+#define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
+
+#define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
+
+/* Fields of DP_DPIDR register */
+#define DP_DPIDR_VERSION_SHIFT 12
+#define DP_DPIDR_VERSION_MASK (0xFUL << DP_DPIDR_VERSION_SHIFT)
/* Fields of the DP's AP ABORT register */
#define DAPABORT (1UL << 0)
#define CSYSPWRUPREQ (1UL << 30)
#define CSYSPWRUPACK (1UL << 31)
+#define DP_DLPIDR_PROTVSN 1u
+
+#define DP_SELECT_APSEL 0xFF000000
+#define DP_SELECT_APBANK 0x000000F0
+#define DP_SELECT_DPBANK 0x0000000F
+#define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
+
+#define DP_APSEL_MAX (255)
+#define DP_APSEL_INVALID (-1)
+
+#define DP_TARGETSEL_INVALID 0xFFFFFFFFU
+#define DP_TARGETSEL_DPID_MASK 0x0FFFFFFFU
+#define DP_TARGETSEL_INSTANCEID_MASK 0xF0000000U
+#define DP_TARGETSEL_INSTANCEID_SHIFT 28
+
+
/* MEM-AP register addresses */
#define MEM_AP_REG_CSW 0x00
#define MEM_AP_REG_TAR 0x04
#define AP_REG_IDR 0xFC /* RO: Identification Register */
/* Fields of the MEM-AP's CSW register */
+#define CSW_SIZE_MASK 7
#define CSW_8BIT 0
#define CSW_16BIT 1
#define CSW_32BIT 2
#define CSW_ADDRINC_PACKED (2UL << 4)
#define CSW_DEVICE_EN (1UL << 6)
#define CSW_TRIN_PROG (1UL << 7)
+
+/* All fields in bits 12 and above are implementation-defined
+ * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
+ * Some bits are shared between buses
+ */
#define CSW_SPIDEN (1UL << 23)
-/* 30:24 - implementation-defined! */
-#define CSW_HPROT (1UL << 25) /* ? */
-#define CSW_MASTER_DEBUG (1UL << 29) /* ? */
-#define CSW_SPROT (1UL << 30)
#define CSW_DBGSWENABLE (1UL << 31)
+/* AHB: Privileged */
+#define CSW_AHB_HPROT1 (1UL << 25)
+/* AHB: set HMASTER signals to AHB-AP ID */
+#define CSW_AHB_MASTER_DEBUG (1UL << 29)
+/* AHB5: non-secure access via HNONSEC
+ * AHB3: SBO, UNPREDICTABLE if zero */
+#define CSW_AHB_SPROT (1UL << 30)
+/* AHB: initial value of csw_default */
+#define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
+
+/* AXI: Privileged */
+#define CSW_AXI_ARPROT0_PRIV (1UL << 28)
+/* AXI: Non-secure */
+#define CSW_AXI_ARPROT1_NONSEC (1UL << 29)
+/* AXI: initial value of csw_default */
+#define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
+
+/* APB: initial value of csw_default */
+#define CSW_APB_DEFAULT (CSW_DBGSWENABLE)
+
+/* Fields of the MEM-AP's CFG register */
+#define MEM_AP_REG_CFG_BE BIT(0)
+#define MEM_AP_REG_CFG_LA BIT(1)
+#define MEM_AP_REG_CFG_LD BIT(2)
+#define MEM_AP_REG_CFG_INVALID 0xFFFFFFF8
+
+/* Fields of the MEM-AP's IDR register */
+#define AP_REG_IDR_REVISION_MASK (0xF0000000)
+#define AP_REG_IDR_REVISION_SHIFT (28)
+#define AP_REG_IDR_DESIGNER_MASK (0x0FFE0000)
+#define AP_REG_IDR_DESIGNER_SHIFT (17)
+#define AP_REG_IDR_CLASS_MASK (0x0001E000)
+#define AP_REG_IDR_CLASS_SHIFT (13)
+#define AP_REG_IDR_VARIANT_MASK (0x000000F0)
+#define AP_REG_IDR_VARIANT_SHIFT (4)
+#define AP_REG_IDR_TYPE_MASK (0x0000000F)
+#define AP_REG_IDR_TYPE_SHIFT (0)
+
+#define AP_REG_IDR_CLASS_NONE (0x0)
+#define AP_REG_IDR_CLASS_COM (0x1)
+#define AP_REG_IDR_CLASS_MEM_AP (0x8)
+
+#define AP_REG_IDR_VALUE(d, c, t) (\
+ (((d) << AP_REG_IDR_DESIGNER_SHIFT) & AP_REG_IDR_DESIGNER_MASK) | \
+ (((c) << AP_REG_IDR_CLASS_SHIFT) & AP_REG_IDR_CLASS_MASK) | \
+ (((t) << AP_REG_IDR_TYPE_SHIFT) & AP_REG_IDR_TYPE_MASK) \
+)
+
+#define AP_TYPE_MASK (AP_REG_IDR_DESIGNER_MASK | AP_REG_IDR_CLASS_MASK | AP_REG_IDR_TYPE_MASK)
+
+/* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
+enum swd_special_seq {
+ LINE_RESET,
+ JTAG_TO_SWD,
+ JTAG_TO_DORMANT,
+ SWD_TO_JTAG,
+ SWD_TO_DORMANT,
+ DORMANT_TO_SWD,
+ DORMANT_TO_JTAG,
+};
+
/**
* This represents an ARM Debug Interface (v5) Access Port (AP).
* Most common is a MEM-AP, for memory access.
*/
struct adiv5_ap {
+ /**
+ * DAP this AP belongs to.
+ */
+ struct adiv5_dap *dap;
+
+ /**
+ * Number of this AP.
+ */
+ uint8_t ap_num;
+
/**
* Default value for (MEM-AP) AP_REG_CSW register.
*/
* configure the address being read or written
* "-1" indicates no cached value.
*/
- uint32_t tar_value;
+ target_addr_t tar_value;
/**
* Configures how many extra tck clocks are added after starting a
/* true if unaligned memory access is not supported by the MEM-AP */
bool unaligned_access_bad;
+
+ /* true if tar_value is in sync with TAR register */
+ bool tar_valid;
+
+ /* MEM AP configuration register indicating LPAE support */
+ uint32_t cfg_reg;
};
struct adiv5_dap {
const struct dap_ops *ops;
- struct arm_jtag *jtag_info;
+ /* dap transaction list for WAIT support */
+ struct list_head cmd_journal;
+
+ /* pool for dap_cmd objects */
+ struct list_head cmd_pool;
+
+ /* number of dap_cmd objects in the pool */
+ size_t cmd_pool_size;
+
+ struct jtag_tap *tap;
/* Control config */
uint32_t dp_ctrl_stat;
- struct adiv5_ap ap[256];
+ struct adiv5_ap ap[DP_APSEL_MAX + 1];
/* The current manually selected AP by the "dap apsel" command */
uint32_t apsel;
/**
- * Cache for DP_SELECT bits identifying the current AP. A DAP may
- * connect to multiple APs, such as one MEM-AP for general access,
- * another reserved for accessing debug modules, and a JTAG-DP.
- * "-1" indicates no cached value.
- */
- uint32_t ap_current;
-
- /**
- * Cache for DP_SELECT bits identifying the current four-word AP
- * register bank. This caches AP register addresss bits 7:4; JTAG
- * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
- * "-1" indicates no cached value.
- */
- uint32_t ap_bank_value;
-
- /**
- * Cache for DP_SELECT bits identifying the current four-word DP
- * register bank. This caches DP register addresss bits 7:4; JTAG
- * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
+ * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
+ * indicates no cached value and forces rewrite of the register.
*/
- uint32_t dp_bank_value;
+ uint32_t select;
/* information about current pending SWjDP-AHBAP transaction */
uint8_t ack;
* swizzle appropriately. */
bool ti_be_32_quirks;
+ /**
+ * STLINK adapter need to know if last AP operation was read or write, and
+ * in case of write has to flush it with a dummy read from DP_RDBUFF
+ */
+ bool stlink_flush_ap_write;
+
/**
* Signals that an attempt to reestablish communication afresh
* should be performed before the next access.
*/
bool do_reconnect;
+
+ /** Flag saying whether to ignore the syspwrupack flag in DAP. Some devices
+ * do not set this bit until later in the bringup sequence */
+ bool ignore_syspwrupack;
+
+ /** Value to select DP in SWD multidrop mode or DP_TARGETSEL_INVALID */
+ uint32_t multidrop_targetsel;
+ /** TPARTNO and TDESIGNER fields of multidrop_targetsel have been configured */
+ bool multidrop_dp_id_valid;
+ /** TINSTANCE field of multidrop_targetsel has been configured */
+ bool multidrop_instance_id_valid;
};
/**
* available until run().
*/
struct dap_ops {
- /** If the DAP transport isn't SWD, it must be JTAG. Upper level
- * code may need to care about the difference in some cases.
- */
- bool is_swd;
+ /** connect operation for SWD */
+ int (*connect)(struct adiv5_dap *dap);
+
+ /** send a sequence to the DAP */
+ int (*send_sequence)(struct adiv5_dap *dap, enum swd_special_seq seq);
/** DP register read. */
int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
uint32_t data);
/** AP register read. */
- int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
+ int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
uint32_t *data);
/** AP register write. */
- int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
+ int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
uint32_t data);
/** AP operation abort. */
/** Executes all queued DAP operations. */
int (*run)(struct adiv5_dap *dap);
+
+ /** Executes all queued DAP operations but doesn't check
+ * sticky error conditions */
+ int (*sync)(struct adiv5_dap *dap);
+
+ /** Optional; called at OpenOCD exit */
+ void (*quit)(struct adiv5_dap *dap);
};
/*
* Access Port types
*/
enum ap_type {
- AP_TYPE_AHB_AP = 0x01, /* AHB Memory-AP */
- AP_TYPE_APB_AP = 0x02, /* APB Memory-AP */
- AP_TYPE_JTAG_AP = 0x10 /* JTAG-AP - JTAG master for controlling other JTAG devices */
+ AP_TYPE_JTAG_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_NONE, 0), /* JTAG-AP */
+ AP_TYPE_COM_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_COM, 0), /* COM-AP */
+ AP_TYPE_AHB3_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 1), /* AHB3 Memory-AP */
+ AP_TYPE_APB_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 2), /* APB2 or APB3 Memory-AP */
+ AP_TYPE_AXI_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 4), /* AXI3 or AXI4 Memory-AP */
+ AP_TYPE_AHB5_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 5), /* AHB5 Memory-AP */
+ AP_TYPE_APB4_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 6), /* APB4 Memory-AP */
+ AP_TYPE_AXI5_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 7), /* AXI5 Memory-AP */
+ AP_TYPE_AHB5H_AP = AP_REG_IDR_VALUE(ARM_ID, AP_REG_IDR_CLASS_MEM_AP, 8), /* AHB5 with enhanced HPROT Memory-AP */
};
+/* Check the ap->cfg_reg Long Address field (bit 1)
+ *
+ * 0b0: The AP only supports physical addresses 32 bits or smaller
+ * 0b1: The AP supports physical addresses larger than 32 bits
+ *
+ * @param ap The AP used for reading.
+ *
+ * @return true for 64 bit, false for 32 bit
+ */
+static inline bool is_64bit_ap(struct adiv5_ap *ap)
+{
+ return (ap->cfg_reg & MEM_AP_REG_CFG_LA) != 0;
+}
+
+/**
+ * Send an adi-v5 sequence to the DAP.
+ *
+ * @param dap The DAP used for reading.
+ * @param seq The sequence to send.
+ *
+ * @return ERROR_OK for success, else a fault code.
+ */
+static inline int dap_send_sequence(struct adiv5_dap *dap,
+ enum swd_special_seq seq)
+{
+ assert(dap->ops);
+ return dap->ops->send_sequence(dap, seq);
+}
+
/**
* Queue a DP register read.
* Note that not all DP registers are readable; also, that JTAG and SWD
static inline int dap_queue_dp_read(struct adiv5_dap *dap,
unsigned reg, uint32_t *data)
{
- assert(dap->ops != NULL);
+ assert(dap->ops);
return dap->ops->queue_dp_read(dap, reg, data);
}
static inline int dap_queue_dp_write(struct adiv5_dap *dap,
unsigned reg, uint32_t data)
{
- assert(dap->ops != NULL);
+ assert(dap->ops);
return dap->ops->queue_dp_write(dap, reg, data);
}
/**
* Queue an AP register read.
*
- * @param dap The DAP used for reading.
+ * @param ap The AP used for reading.
* @param reg The number of the AP register being read.
* @param data Pointer saying where to store the register's value
* (in host endianness).
*
* @return ERROR_OK for success, else a fault code.
*/
-static inline int dap_queue_ap_read(struct adiv5_dap *dap,
+static inline int dap_queue_ap_read(struct adiv5_ap *ap,
unsigned reg, uint32_t *data)
{
- assert(dap->ops != NULL);
- return dap->ops->queue_ap_read(dap, reg, data);
+ assert(ap->dap->ops);
+ return ap->dap->ops->queue_ap_read(ap, reg, data);
}
/**
* Queue an AP register write.
*
- * @param dap The DAP used for writing.
+ * @param ap The AP used for writing.
* @param reg The number of the AP register being written.
* @param data Value being written (host endianness)
*
* @return ERROR_OK for success, else a fault code.
*/
-static inline int dap_queue_ap_write(struct adiv5_dap *dap,
+static inline int dap_queue_ap_write(struct adiv5_ap *ap,
unsigned reg, uint32_t data)
{
- assert(dap->ops != NULL);
- return dap->ops->queue_ap_write(dap, reg, data);
+ assert(ap->dap->ops);
+ return ap->dap->ops->queue_ap_write(ap, reg, data);
}
/**
*/
static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
{
- assert(dap->ops != NULL);
+ assert(dap->ops);
return dap->ops->queue_ap_abort(dap, ack);
}
*/
static inline int dap_run(struct adiv5_dap *dap)
{
- assert(dap->ops != NULL);
+ assert(dap->ops);
return dap->ops->run(dap);
}
+static inline int dap_sync(struct adiv5_dap *dap)
+{
+ assert(dap->ops);
+ if (dap->ops->sync)
+ return dap->ops->sync(dap);
+ return ERROR_OK;
+}
+
static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
uint32_t *value)
{
}
}
-/** Accessor for currently selected DAP-AP number (0..255) */
-static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
-{
- return (uint8_t)(swjdp->ap_current >> 24);
-}
-
-/* AP selection applies to future AP transactions */
-void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
-
-/* Queued AP transactions */
-int dap_setup_accessport(struct adiv5_dap *swjdp,
- uint32_t csw, uint32_t tar);
-
-/* Queued MEM-AP memory mapped single word transfers with selection of ap */
-int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
- uint32_t address, uint32_t *value);
-int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
- uint32_t address, uint32_t value);
-
-/* Synchronous MEM-AP memory mapped single word transfers with selection of ap */
-int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
- uint32_t address, uint32_t *value);
-int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
- uint32_t address, uint32_t value);
-
-/* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */
-int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
- uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
-int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
- const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
-
-/* Synchronous, non-incrementing buffer functions for accessing fifos, with
- * selection of ap */
-int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
- uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
-int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
- const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
-
-/* Create DAP struct */
-struct adiv5_dap *dap_init(void);
+/* Queued MEM-AP memory mapped single word transfers. */
+int mem_ap_read_u32(struct adiv5_ap *ap,
+ target_addr_t address, uint32_t *value);
+int mem_ap_write_u32(struct adiv5_ap *ap,
+ target_addr_t address, uint32_t value);
+
+/* Synchronous MEM-AP memory mapped single word transfers. */
+int mem_ap_read_atomic_u32(struct adiv5_ap *ap,
+ target_addr_t address, uint32_t *value);
+int mem_ap_write_atomic_u32(struct adiv5_ap *ap,
+ target_addr_t address, uint32_t value);
+
+/* Synchronous MEM-AP memory mapped bus block transfers. */
+int mem_ap_read_buf(struct adiv5_ap *ap,
+ uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
+int mem_ap_write_buf(struct adiv5_ap *ap,
+ const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
+
+/* Synchronous, non-incrementing buffer functions for accessing fifos. */
+int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
+ uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
+int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
+ const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
/* Initialisation of the debug system, power domains and registers */
-int ahbap_debugport_init(struct adiv5_dap *swjdp, uint8_t apsel);
+int dap_dp_init(struct adiv5_dap *dap);
+int dap_dp_init_or_reconnect(struct adiv5_dap *dap);
+int mem_ap_init(struct adiv5_ap *ap);
+
+/* Invalidate cached DP select and cached TAR and CSW of all APs */
+void dap_invalidate_cache(struct adiv5_dap *dap);
/* Probe the AP for ROM Table location */
-int dap_get_debugbase(struct adiv5_dap *dap, int ap,
- uint32_t *dbgbase, uint32_t *apid);
+int dap_get_debugbase(struct adiv5_ap *ap,
+ target_addr_t *dbgbase, uint32_t *apid);
/* Probe Access Ports to find a particular type */
int dap_find_ap(struct adiv5_dap *dap,
enum ap_type type_to_find,
- uint8_t *ap_num_out);
+ struct adiv5_ap **ap_out);
+
+static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num)
+{
+ return &dap->ap[ap_num];
+}
+
+/** Check if SWD multidrop configuration is valid */
+static inline bool dap_is_multidrop(struct adiv5_dap *dap)
+{
+ return dap->multidrop_dp_id_valid && dap->multidrop_instance_id_valid;
+}
/* Lookup CoreSight component */
-int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
- uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);
+int dap_lookup_cs_component(struct adiv5_ap *ap,
+ target_addr_t dbgbase, uint8_t type, target_addr_t *addr, int32_t *idx);
struct target;
/* Put debug link into SWD mode */
-int dap_to_swd(struct target *target);
+int dap_to_swd(struct adiv5_dap *dap);
/* Put debug link into JTAG mode */
-int dap_to_jtag(struct target *target);
+int dap_to_jtag(struct adiv5_dap *dap);
+
+extern const struct command_registration dap_instance_commands[];
+
+struct arm_dap_object;
+extern struct adiv5_dap *dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o);
+extern struct adiv5_dap *adiv5_get_dap(struct arm_dap_object *obj);
+extern int dap_info_command(struct command_invocation *cmd,
+ struct adiv5_ap *ap);
+extern int dap_register_commands(struct command_context *cmd_ctx);
+extern const char *adiv5_dap_name(struct adiv5_dap *self);
+extern const struct swd_driver *adiv5_dap_swd_driver(struct adiv5_dap *self);
+extern int dap_cleanup_all(void);
+
+struct adiv5_private_config {
+ int ap_num;
+ struct adiv5_dap *dap;
+};
+
+extern int adiv5_verify_config(struct adiv5_private_config *pc);
+extern int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi);
+
+struct adiv5_mem_ap_spot {
+ struct adiv5_dap *dap;
+ int ap_num;
+ uint32_t base;
+};
-extern const struct command_registration dap_command_handlers[];
+extern int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p);
+extern int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot *cfg,
+ struct jim_getopt_info *goi);
-#endif
+#endif /* OPENOCD_TARGET_ARM_ADI_V5_H */
projects / fw / openocd / blobdiff