cortex_a: fix endiannes issues on TI TMS570

[fw/openocd] / src / target / arm_adi_v5.h

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index cdcf928a025d1370465fed2de694ba56073e4392..3367588f74121f7a067913ee548c31078ee36abe 100644 (file)
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -189,6 +189,15 @@ struct adiv5_dap {
 
        /* true if packed transfers are supported by the MEM-AP */
        bool packed_transfers;
+
+       /* true if unaligned memory access is not supported by the MEM-AP */
+       bool unaligned_access_bad;
+
+       /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
+        * despite lack of support in the ARMv7 architecture. Memory access through
+        * the AHB-AP has strange byte ordering these processors, and we need to
+        * swizzle appropriately. */
+       bool ti_be_32_quirks;
 };
 
 /**