* @param apsel Number of the AP to (implicitly) use with further
* transactions. This normally identifies a MEM-AP.
*/
-void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel)
+void dap_ap_select(struct adiv5_dap *dap,uint8_t ap)
{
- uint32_t select_apsel = (apsel << 24) & 0xFF000000;
+ uint32_t new_ap = (ap << 24) & 0xFF000000;
- if (select_apsel != dap->apsel)
+ if (new_ap != dap->ap_current)
{
- dap->apsel = select_apsel;
+ dap->ap_current = new_ap;
/* Switching AP invalidates cached values.
* Values MUST BE UPDATED BEFORE AP ACCESS.
*/
* Write a buffer in target order (little endian) *
* *
*****************************************************************************/
-int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
{
int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
uint32_t adr = address;
- uint8_t* pBuffer = buffer;
+ const uint8_t* pBuffer = buffer;
count >>= 2;
wcount = count;
for (writecount = 0; writecount < blocksize; writecount++)
{
retval = dap_queue_ap_write(dap, AP_REG_DRW,
- *(uint32_t *) (buffer + 4 * writecount));
+ *(uint32_t *) ((void *) (buffer + 4 * writecount)));
if (retval != ERROR_OK)
break;
}
- if (dap_run(dap) == ERROR_OK)
+ if ((retval = dap_run(dap)) == ERROR_OK)
{
wcount = wcount - blocksize;
address = address + 4 * blocksize;
if (errorcount > 1)
{
LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
- /* REVISIT return the *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
}
}
static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
- uint8_t *buffer, int count, uint32_t address)
+ const uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
int wcount, blocksize, writecount, i;
if (retval != ERROR_OK)
break;
- if (dap_run(dap) != ERROR_OK)
+ if ((retval = dap_run(dap)) != ERROR_OK)
{
LOG_WARNING("Block write error address "
"0x%" PRIx32 ", count 0x%x",
address, count);
- /* REVISIT return *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
}
return retval;
}
-int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
}
static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
- uint8_t *buffer, int count, uint32_t address)
+ const uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
int wcount, blocksize, writecount, i;
if (retval != ERROR_OK)
break;
- if (dap_run(dap) != ERROR_OK)
+ if ((retval = dap_run(dap)) != ERROR_OK)
{
LOG_WARNING("Block write error address "
"0x%" PRIx32 ", count 0x%x",
address, count);
- /* REVISIT return *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
}
return retval;
}
-int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
do
{
retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
- if (dap_run(dap) != ERROR_OK)
+ if (retval != ERROR_OK)
+ return retval;
+ if ((retval = dap_run(dap)) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
- /* REVISIT return the *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
nbytes = MIN((readcount << 1), 4);
do
{
retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
- if (dap_run(dap) != ERROR_OK)
+ if (retval != ERROR_OK)
+ return retval;
+ if ((retval = dap_run(dap)) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
- /* REVISIT return the *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ return retval;
}
nbytes = MIN(readcount, 4);
return retval;
}
+/*--------------------------------------------------------------------*/
+/* Wrapping function with selection of AP */
+/*--------------------------------------------------------------------*/
+int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
+ uint32_t address, uint32_t *value)
+{
+ dap_ap_select(swjdp, ap);
+ return mem_ap_read_u32(swjdp, address, value);
+}
+
+int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
+ uint32_t address, uint32_t value)
+{
+ dap_ap_select(swjdp, ap);
+ return mem_ap_write_u32(swjdp, address, value);
+}
+
+int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
+ uint32_t address, uint32_t *value)
+{
+ dap_ap_select(swjdp, ap);
+ return mem_ap_read_atomic_u32(swjdp, address, value);
+}
+
+int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
+ uint32_t address, uint32_t value)
+{
+ dap_ap_select(swjdp, ap);
+ return mem_ap_write_atomic_u32(swjdp, address, value);
+}
+
+int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
+ uint8_t *buffer, int count, uint32_t address)
+{
+ dap_ap_select(swjdp, ap);
+ return mem_ap_read_buf_u8(swjdp, buffer, count, address);
+}
+
+int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
+ uint8_t *buffer, int count, uint32_t address)
+{
+ dap_ap_select(swjdp, ap);
+ return mem_ap_read_buf_u16(swjdp, buffer, count, address);
+}
+
+int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
+ uint8_t *buffer, int count, uint32_t address)
+{
+ dap_ap_select(swjdp, ap);
+ return mem_ap_read_buf_u32(swjdp, buffer, count, address);
+}
+
+int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
+ const uint8_t *buffer, int count, uint32_t address)
+{
+ dap_ap_select(swjdp, ap);
+ return mem_ap_write_buf_u8(swjdp, buffer, count, address);
+}
+
+int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
+ const uint8_t *buffer, int count, uint32_t address)
+{
+ dap_ap_select(swjdp, ap);
+ return mem_ap_write_buf_u16(swjdp, buffer, count, address);
+}
+
+int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
+ const uint8_t *buffer, int count, uint32_t address)
+{
+ dap_ap_select(swjdp, ap);
+ return mem_ap_write_buf_u32(swjdp, buffer, count, address);
+}
+
+
/*--------------------------------------------------------------------------*/
*/
int ahbap_debugport_init(struct adiv5_dap *dap)
{
- uint32_t idreg, romaddr, dummy;
uint32_t ctrlstat;
int cnt = 0;
int retval;
LOG_DEBUG(" ");
- /* JTAG-DP or SWJ-DP, in JTAG mode */
- dap->ops = &jtag_dp_ops;
+ /* JTAG-DP or SWJ-DP, in JTAG mode
+ * ... for SWD mode this is patched as part
+ * of link switchover
+ */
+ if (!dap->ops)
+ dap->ops = &jtag_dp_ops;
/* Default MEM-AP setup.
*
* Should we probe, or take a hint from the caller?
* Presumably we can ignore the possibility of multiple APs.
*/
- dap->apsel = !0;
+ dap->ap_current = !0;
dap_ap_select(dap, 0);
/* DP initialization */
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
if (retval != ERROR_OK)
return retval;
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
if (retval != ERROR_OK)
return retval;
alive_sleep(10);
}
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
if (retval != ERROR_OK)
return retval;
/* With debug power on we can activate OVERRUN checking */
retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
if (retval != ERROR_OK)
return retval;
- /*
- * REVISIT this isn't actually *initializing* anything in an AP,
- * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
- * Should it? If the ROM address is valid, is this the right
- * place to scan the table and do any topology detection?
- */
- retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg);
- retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr);
-
- if ((retval = dap_run(dap)) != ERROR_OK)
- return retval;
-
- LOG_DEBUG("MEM-AP #%" PRId32 " ID Register 0x%" PRIx32
- ", Debug ROM Address 0x%" PRIx32,
- dap->apsel, idreg, romaddr);
-
return ERROR_OK;
}
&& ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
}
-static int dap_info_command(struct command_context *cmd_ctx,
- struct adiv5_dap *dap, int apsel)
+int dap_get_debugbase(struct adiv5_dap *dap, int ap,
+ uint32_t *out_dbgbase, uint32_t *out_apid)
{
+ uint32_t ap_old;
int retval;
uint32_t dbgbase, apid;
- int romtable_present = 0;
- uint8_t mem_ap;
- uint32_t apselold;
/* AP address is in bits 31:24 of DP_SELECT */
- if (apsel >= 256)
+ if (ap >= 256)
return ERROR_INVALID_ARGUMENTS;
- apselold = dap->apsel;
- dap_ap_select(dap, apsel);
+ ap_old = dap->ap_current;
+ dap_ap_select(dap, ap);
+
retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
+ /* Excavate the device ID code */
+ struct jtag_tap *tap = dap->jtag_info->tap;
+ while (tap != NULL) {
+ if (tap->hasidcode)
+ break;
+ tap = tap->next_tap;
+ }
+ if (tap == NULL || !tap->hasidcode)
+ return ERROR_OK;
+
+ dap_ap_select(dap, ap_old);
+
+ /* The asignment happens only here to prevent modification of these
+ * values before they are certain. */
+ *out_dbgbase = dbgbase;
+ *out_apid = apid;
+
+ return ERROR_OK;
+}
+
+int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
+ uint32_t dbgbase, uint8_t type, uint32_t *addr)
+{
+ uint32_t ap_old;
+ uint32_t romentry, entry_offset = 0, component_base, devtype;
+ int retval = ERROR_FAIL;
+
+ if (ap >= 256)
+ return ERROR_INVALID_ARGUMENTS;
+
+ ap_old = dap->ap_current;
+ dap_ap_select(dap, ap);
+
+ do
+ {
+ retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
+ entry_offset, &romentry);
+ if (retval != ERROR_OK)
+ return retval;
+
+ component_base = (dbgbase & 0xFFFFF000)
+ + (romentry & 0xFFFFF000);
+
+ if (romentry & 0x1) {
+ retval = mem_ap_read_atomic_u32(dap,
+ (component_base & 0xfffff000) | 0xfcc,
+ &devtype);
+ if ((devtype & 0xff) == type) {
+ *addr = component_base;
+ retval = ERROR_OK;
+ break;
+ }
+ }
+ entry_offset += 4;
+ } while (romentry > 0);
+
+ dap_ap_select(dap, ap_old);
+
+ return retval;
+}
+
+static int dap_info_command(struct command_context *cmd_ctx,
+ struct adiv5_dap *dap, int ap)
+{
+ int retval;
+ uint32_t dbgbase, apid;
+ int romtable_present = 0;
+ uint8_t mem_ap;
+ uint32_t ap_old;
+
+ retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
+ if (retval != ERROR_OK)
+ return retval;
+
+ ap_old = dap->ap_current;
+ dap_ap_select(dap, ap);
+
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
}
else
{
- command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
+ command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
}
romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
/* Part number interpretations are from Cortex
* core specs, the CoreSight components TRM
- * (ARM DDI 0314H), and ETM specs; also from
- * chip observation (e.g. TI SDTI).
+ * (ARM DDI 0314H), CoreSight System Design
+ * Guide (ARM DGI 0012D) and ETM specs; also
+ * from chip observation (e.g. TI SDTI).
*/
part_num = (c_pid0 & 0xff);
part_num |= (c_pid1 & 0x0f) << 8;
type = "Cortex-M3 ETM";
full = "(Embedded Trace)";
break;
+ case 0x930:
+ type = "Cortex-R4 ETM";
+ full = "(Embedded Trace)";
+ break;
case 0xc08:
type = "Cortex-A8 Debug";
full = "(Debug Unit)";
{
command_print(cmd_ctx, "\tNo ROM table present");
}
- dap_ap_select(dap, apselold);
+ dap_ap_select(dap, ap_old);
return ERROR_OK;
}
struct arm *arm = target_to_arm(target);
struct adiv5_dap *dap = arm->dap;
- uint32_t apsel, apselsave, baseaddr;
+ uint32_t apsel, baseaddr;
int retval;
- apselsave = dap->apsel;
switch (CMD_ARGC) {
case 0:
apsel = dap->apsel;
return ERROR_COMMAND_SYNTAX_ERROR;
}
- if (apselsave != apsel)
- dap_ap_select(dap, apsel);
+ dap_ap_select(dap, apsel);
/* NOTE: assumes we're talking to a MEM-AP, which
* has a base address. There are other kinds of AP,
* use the ID register to verify it's a MEM-AP.
*/
retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
- if (apselsave != apsel)
- dap_ap_select(dap, apselsave);
-
return retval;
}
return ERROR_COMMAND_SYNTAX_ERROR;
}
+ dap->apsel = apsel;
dap_ap_select(dap, apsel);
+
retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
struct arm *arm = target_to_arm(target);
struct adiv5_dap *dap = arm->dap;
- uint32_t apsel, apselsave, apid;
+ uint32_t apsel, apid;
int retval;
- apselsave = dap->apsel;
switch (CMD_ARGC) {
case 0:
apsel = dap->apsel;
return ERROR_COMMAND_SYNTAX_ERROR;
}
- if (apselsave != apsel)
- dap_ap_select(dap, apsel);
+ dap_ap_select(dap, apsel);
retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
- if (apselsave != apsel)
- dap_ap_select(dap, apselsave);
return retval;
}
projects / fw / openocd / blobdiff