* *
* ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A *
* *
- * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A *
- * Cortex-M3(tm) TRM, ARM DDI 0337C *
+ * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D *
+ * Cortex-M3(tm) TRM, ARM DDI 0337G *
* *
***************************************************************************/
arm_jtag_set_instr(jtag_info, instr, NULL);
/* Add specified number of tck clocks before accessing memory bus */
- if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0) )&& (swjdp->memaccess_tck != 0))
+ if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0))
jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
fields[0].tap = jtag_info->tap;
arm_jtag_set_instr(jtag_info, instr, NULL);
/* Add specified number of tck clocks before accessing memory bus */
- if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0) )&& (swjdp->memaccess_tck != 0))
+ if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0))
jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
fields[0].tap = jtag_info->tap;
adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
}
- /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
+ /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and the check CTRL_STAT */
if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
{
return swjdp_transaction_endcheck(swjdp);
{
adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
- if ((RnW==DPAP_READ) && (invalue != NULL))
+ if ((RnW == DPAP_READ) && (invalue != NULL))
{
adi_jtag_dp_scan_u32(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
}
- /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
+ /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and then check CTRL_STAT */
if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
{
return swjdp_transaction_endcheck(swjdp);
https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
*/
- if ((retval=jtag_execute_queue()) != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("BUG: Why does this fail the first time????");
}
#endif
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue()) != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
swjdp->ack = swjdp->ack & 0x7;
if (swjdp->ack != 2)
{
- long long then=timeval_ms();
+ long long then = timeval_ms();
while (swjdp->ack != 2)
{
if (swjdp->ack == 1)
}
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue()) != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
swjdp->ack = swjdp->ack & 0x7;
}
/* Clear Sticky Error Bits */
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue()) != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
- if ((retval=jtag_execute_queue()) != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
}
- if ((retval=jtag_execute_queue()) != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
return ERROR_JTAG_DEVICE_ERROR;
}
if (csw != swjdp->ap_csw_value)
{
/* LOG_DEBUG("swjdp : Set CSW %x",csw); */
- dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw );
+ dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
swjdp->ap_csw_value = csw;
}
if (tar != swjdp->ap_tar_value)
{
/* LOG_DEBUG("swjdp : Set TAR %x",tar); */
- dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar );
+ dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
swjdp->ap_tar_value = tar;
}
if (csw & CSW_ADDRINC_MASK)
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
- dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
+ dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
return ERROR_OK;
}
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
- dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
return ERROR_OK;
}
uint32_t outvalue;
memcpy(&outvalue, pBuffer, sizeof(uint32_t));
- for (i = 0; i < 4; i++ )
+ for (i = 0; i < 4; i++)
{
*((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
outvalue >>= 8;
for (writecount = 0; writecount < blocksize; writecount++)
{
- dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount );
+ dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
}
if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
{
nbytes = MIN((writecount << 1), 4);
- if (nbytes < 4 )
+ if (nbytes < 4)
{
if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
{
uint32_t outvalue;
memcpy(&outvalue, buffer, sizeof(uint32_t));
- for (i = 0; i < nbytes; i++ )
+ for (i = 0; i < nbytes; i++)
{
*((uint8_t*)buffer + (address & 0x3)) = outvalue;
outvalue >>= 8;
uint16_t svalue;
memcpy(&svalue, buffer, sizeof(uint16_t));
uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
- dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
+ dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
retval = swjdp_transaction_endcheck(swjdp);
count -= 2;
address += 2;
{
nbytes = MIN(writecount, 4);
- if (nbytes < 4 )
+ if (nbytes < 4)
{
if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
{
uint32_t outvalue;
memcpy(&outvalue, buffer, sizeof(uint32_t));
- for (i = 0; i < nbytes; i++ )
+ for (i = 0; i < nbytes; i++)
{
*((uint8_t*)buffer + (address & 0x3)) = outvalue;
outvalue >>= 8;
{
dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
- dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
+ dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
retval = swjdp_transaction_endcheck(swjdp);
count--;
address++;
uint32_t data;
memcpy(&data, pBuffer, sizeof(uint32_t));
- for (i = 0; i < 4; i++ )
+ for (i = 0; i < 4; i++)
{
*((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
pBuffer++;
do
{
- dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
+ dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
nbytes = MIN((readcount << 1), 4);
- for (i = 0; i < nbytes; i++ )
+ for (i = 0; i < nbytes; i++)
{
*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
buffer++;
while (count > 0)
{
dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
- dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
+ dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
retval = swjdp_transaction_endcheck(swjdp);
if (address & 0x1)
{
- for (i = 0; i < 2; i++ )
+ for (i = 0; i < 2; i++)
{
*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
buffer++;
do
{
- dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
+ dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
nbytes = MIN(readcount, 4);
- for (i = 0; i < nbytes; i++ )
+ for (i = 0; i < nbytes; i++)
{
*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
buffer++;
while (count > 0)
{
dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
- dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
+ dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
retval = swjdp_transaction_endcheck(swjdp);
*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
count--;
dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue()) != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
/* Check that we have debug power domains activated */
{
LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue()) != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
alive_sleep(10);
}
{
LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue()) != ERROR_OK)
+ if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
alive_sleep(10);
}
}
else
{
- command_print(cmd_ctx, "\tROM table in legacy format" );
+ command_print(cmd_ctx, "\tROM table in legacy format");
}
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF0, &cid0);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF4, &cid1);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF8, &cid2);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFFC, &cid3);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFCC, &memtype);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
swjdp_transaction_endcheck(swjdp);
command_print(cmd_ctx, "\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 " CID0, 0x%" PRIx32,cid3,cid2,cid1,cid0);
if (memtype&0x01)
}
else
{
- command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus" );
+ command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus");
}
- /* Now we read ROM table entries from dbgbase&0xFFFFF000)|0x000 until we get 0x00000000 */
+ /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
entry_offset = 0;
do
{
- mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000)|entry_offset, &romentry);
+ mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
if (romentry&0x01)
{
uint32_t c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start;
- uint32_t component_base = (uint32_t)((dbgbase&0xFFFFF000)+(int)(romentry&0xFFFFF000));
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE0, &c_pid0);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE4, &c_pid1);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE8, &c_pid2);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFEC, &c_pid3);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFD0, &c_pid4);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF0, &c_cid0);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3);
+ uint32_t component_base = (uint32_t)((dbgbase&0xFFFFF000) + (int)(romentry&0xFFFFF000));
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE0, &c_pid0);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE4, &c_pid1);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE8, &c_pid2);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFEC, &c_pid3);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFD0, &c_pid4);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF0, &c_cid0);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF4, &c_cid1);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF8, &c_cid2);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFFC, &c_cid3);
component_start = component_base - 0x1000*(c_pid4 >> 4);
command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", pid4 0x%" PRIx32 ", start address 0x%" PRIx32 "",component_base,c_pid4,component_start);
command_print(cmd_ctx, "\t\tComponent cid1 0x%" PRIx32 ", class is %s",c_cid1,class_description[(c_cid1 >> 4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
command_print(cmd_ctx, "\t\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 ", CID0, 0x%" PRIx32 "",c_cid3,c_cid2,c_cid1,c_cid0);
command_print(cmd_ctx, "\t\tPID3 0x%" PRIx32 ", PID2 0x%" PRIx32 ", PID1 0x%" PRIx32 ", PID0, 0x%" PRIx32 "",c_pid3,c_pid2,c_pid1,c_pid0);
- /* For CoreSight components, (c_cid1 >> 4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */
+ /* For CoreSight components, (c_cid1 >> 4)&0xF == 9 , we also read 0xFC8 DevId and 0xFCC DevType */
}
else
{
command_print(cmd_ctx, "\t\tEnd of ROM table");
}
entry_offset += 4;
- } while (romentry>0);
+ } while (romentry > 0);
}
else
{
return ERROR_OK;
}
+int dap_baseaddr_command(struct command_context_s *cmd_ctx,
+ swjdp_common_t *swjdp, char **args, int argc)
+{
+ uint32_t apsel, apselsave, baseaddr;
+ int retval;
+
+ apsel = swjdp->apsel;
+ apselsave = swjdp->apsel;
+ if (argc > 0)
+ apsel = strtoul(args[0], NULL, 0);
+ if (apselsave != apsel)
+ dap_ap_select(swjdp, apsel);
+
+ dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "0x%8.8" PRIx32, baseaddr);
+
+ if (apselsave != apsel)
+ dap_ap_select(swjdp, apselsave);
+
+ return retval;
+}
+
+int dap_memaccess_command(struct command_context_s *cmd_ctx,
+ swjdp_common_t *swjdp, char **args, int argc)
+{
+ uint32_t memaccess_tck;
+
+ memaccess_tck = swjdp->memaccess_tck;
+ if (argc > 0)
+ memaccess_tck = strtoul(args[0], NULL, 0);
+
+ swjdp->memaccess_tck = memaccess_tck;
+ command_print(cmd_ctx, "memory bus access delay set to %" PRIi32 " tck",
+ swjdp->memaccess_tck);
+
+ return ERROR_OK;
+}
+
+int dap_apsel_command(struct command_context_s *cmd_ctx,
+ swjdp_common_t *swjdp, char **args, int argc)
+{
+ uint32_t apsel, apid;
+ int retval;
+
+ apsel = 0;
+ if (argc > 0)
+ apsel = strtoul(args[0], NULL, 0);
+
+ dap_ap_select(swjdp, apsel);
+ dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
+ apsel, apid);
+
+ return retval;
+}
+
+int dap_apid_command(struct command_context_s *cmd_ctx,
+ swjdp_common_t *swjdp, char **args, int argc)
+{
+ uint32_t apsel, apselsave, apid;
+ int retval;
+
+ apsel = swjdp->apsel;
+ apselsave = swjdp->apsel;
+ if (argc > 0)
+ apsel = strtoul(args[0], NULL, 0);
+
+ if (apselsave != apsel)
+ dap_ap_select(swjdp, apsel);
+
+ dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "0x%8.8" PRIx32, apid);
+ if (apselsave != apsel)
+ dap_ap_select(swjdp, apselsave);
+
+ return retval;
+}
+
+
projects / fw / openocd / blobdiff