return ERROR_OK;
}
-/* CID interpretation -- see ARM IHI 0029B section 3 */
+/* CID interpretation -- see ARM IHI 0029B section 3
+ * and ARM IHI 0031A table 13-3.
+ */
static const char *class_description[16] ={
"Reserved", "ROM table", "Reserved", "Reserved",
"Reserved", "Reserved", "Reserved", "Reserved",
"Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
- "Reserved", "DESS", "Generic IP component", "PrimeCell or System component"
+ "Reserved", "OptimoDE DESS",
+ "Generic IP component", "PrimeCell or System component"
};
static bool
dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
retval = swjdp_transaction_endcheck(swjdp);
- command_print(cmd_ctx, "0x%8.8" PRIx32, baseaddr);
+ command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
if (apselsave != apsel)
dap_ap_select(swjdp, apselsave);
}
swjdp->memaccess_tck = memaccess_tck;
- command_print(cmd_ctx, "memory bus access delay set to %" PRIi32 " tck",
+ command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
swjdp->memaccess_tck);
return ERROR_OK;
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
retval = swjdp_transaction_endcheck(swjdp);
- command_print(cmd_ctx, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
+ command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
apsel, apid);
return retval;
dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
retval = swjdp_transaction_endcheck(swjdp);
- command_print(cmd_ctx, "0x%8.8" PRIx32, apid);
+ command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
if (apselsave != apsel)
dap_ap_select(swjdp, apselsave);