* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
- * Copyright (C) 2009 by Oyvind Harboe *
+ * Copyright (C) 2009-2010 by Oyvind Harboe *
* oyvind.harboe@zylin.com *
* *
* Copyright (C) 2009-2010 by David Brownell *
*/
void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel)
{
- uint32_t select = (apsel << 24) & 0xFF000000;
+ uint32_t select_apsel = (apsel << 24) & 0xFF000000;
- if (select != dap->apsel)
+ if (select_apsel != dap->apsel)
{
- dap->apsel = select;
+ dap->apsel = select_apsel;
/* Switching AP invalidates cached values.
* Values MUST BE UPDATED BEFORE AP ACCESS.
*/
if (blocksize == 0)
blocksize = 1;
- dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
+ retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
+ if (retval != ERROR_OK)
+ return retval;
for (writecount = 0; writecount < blocksize; writecount++)
{
if (blocksize == 0)
blocksize = 1;
- dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+ retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+ if (retval != ERROR_OK)
+ return retval;
writecount = blocksize;
do
while (count > 0)
{
- dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+ retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+ if (retval != ERROR_OK)
+ return retval;
uint16_t svalue;
memcpy(&svalue, buffer, sizeof(uint16_t));
uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
if (wcount < blocksize)
blocksize = wcount;
- dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+ retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+ if (retval != ERROR_OK)
+ return retval;
writecount = blocksize;
do
while (count > 0)
{
- dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+ retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+ if (retval != ERROR_OK)
+ return retval;
uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
if (retval != ERROR_OK)
if (blocksize == 0)
blocksize = 1;
- dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
+ retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
address);
+ if (retval != ERROR_OK)
+ return retval;
/* FIXME remove these three calls to adi_jtag_dp_scan(),
* so this routine becomes transport-neutral. Be careful
*/
/* Scan out first read */
- adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
+ retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
DPAP_READ, 0, NULL, NULL);
+ if (retval != ERROR_OK)
+ return retval;
for (readcount = 0; readcount < blocksize - 1; readcount++)
{
/* Scan out next read; scan in posted value for the
* previous one. Assumes read is acked "OK/FAULT",
* and CTRL_STAT says that meant "OK".
*/
- adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
+ retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
DPAP_READ, 0, buffer + 4 * readcount,
&dap->ack);
+ if (retval != ERROR_OK)
+ return retval;
}
/* Scan in last posted value; RDBUFF has no other effect,
* assuming ack is OK/FAULT and CTRL_STAT says "OK".
*/
- adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
+ retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
DPAP_READ, 0, buffer + 4 * readcount,
&dap->ack);
- if (dap_run(dap) == ERROR_OK)
- {
- wcount = wcount - blocksize;
- address += 4 * blocksize;
- buffer += 4 * blocksize;
- }
- else
- {
- errorcount++;
- }
+ if (retval != ERROR_OK)
+ return retval;
- if (errorcount > 1)
+ retval = dap_run(dap);
+ if (retval != ERROR_OK)
{
- LOG_WARNING("Block read error address 0x%" PRIx32
- ", count 0x%x", address, count);
- /* REVISIT return the *actual* fault code */
- return ERROR_JTAG_DEVICE_ERROR;
+ errorcount++;
+ if (errorcount <= 1)
+ {
+ /* try again */
+ continue;
+ }
+ LOG_WARNING("Block read error address 0x%" PRIx32, address);
+ return retval;
}
+ wcount = wcount - blocksize;
+ address += 4 * blocksize;
+ buffer += 4 * blocksize;
}
/* if we have an unaligned access - reorder data */
if (wcount < blocksize)
blocksize = wcount;
- dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+ retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+ if (retval != ERROR_OK)
+ return retval;
/* handle unaligned data at 4k boundary */
if (blocksize == 0)
while (count > 0)
{
- dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+ retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
if (retval != ERROR_OK)
break;
if (wcount < blocksize)
blocksize = wcount;
- dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+ retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+ if (retval != ERROR_OK)
+ return retval;
readcount = blocksize;
do
while (count > 0)
{
- dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+ retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
break;
command_print(cmd_ctx, "\tROM table in legacy format");
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
- mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
- command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
- ", CID2 0x%2.2" PRIx32
- ", CID1 0x%2.2" PRIx32
- ", CID0 0x%2.2" PRIx32,
- cid3, cid2, cid1, cid0);
+ command_print(cmd_ctx, "\tCID3 0x%2.2x"
+ ", CID2 0x%2.2x"
+ ", CID1 0x%2.2x"
+ ", CID0 0x%2.2x",
+ (unsigned) cid3, (unsigned)cid2,
+ (unsigned) cid1, (unsigned) cid0);
if (memtype & 0x01)
command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
else
{
uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
- uint32_t component_start, component_base;
+ uint32_t component_base;
unsigned part_num;
char *type, *full;
- component_base = (uint32_t)((dbgbase & 0xFFFFF000)
- + (int)(romentry & 0xFFFFF000));
+ component_base = (dbgbase & 0xFFFFF000)
+ + (romentry & 0xFFFFF000);
+
+ /* IDs are in last 4K section */
+
+
mem_ap_read_atomic_u32(dap,
- (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
+ component_base + 0xFE0, &c_pid0);
+ c_pid0 &= 0xff;
mem_ap_read_atomic_u32(dap,
- (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
+ component_base + 0xFE4, &c_pid1);
+ c_pid1 &= 0xff;
mem_ap_read_atomic_u32(dap,
- (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
+ component_base + 0xFE8, &c_pid2);
+ c_pid2 &= 0xff;
mem_ap_read_atomic_u32(dap,
- (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
+ component_base + 0xFEC, &c_pid3);
+ c_pid3 &= 0xff;
mem_ap_read_atomic_u32(dap,
- (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
+ component_base + 0xFD0, &c_pid4);
+ c_pid4 &= 0xff;
+
mem_ap_read_atomic_u32(dap,
- (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
+ component_base + 0xFF0, &c_cid0);
+ c_cid0 &= 0xff;
mem_ap_read_atomic_u32(dap,
- (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
+ component_base + 0xFF4, &c_cid1);
+ c_cid1 &= 0xff;
mem_ap_read_atomic_u32(dap,
- (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
+ component_base + 0xFF8, &c_cid2);
+ c_cid2 &= 0xff;
mem_ap_read_atomic_u32(dap,
- (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
- component_start = component_base - 0x1000*(c_pid4 >> 4);
+ component_base + 0xFFC, &c_cid3);
+ c_cid3 &= 0xff;
+
- command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
- ", start address 0x%" PRIx32,
- component_base, component_start);
+ command_print(cmd_ctx,
+ "\t\tComponent base address 0x%" PRIx32
+ ", start address 0x%" PRIx32,
+ component_base,
+ /* component may take multiple 4K pages */
+ component_base - 0x1000*(c_pid4 >> 4));
command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
(int) (c_cid1 >> 4) & 0xf,
/* See ARM IHI 0029B Table 3-3 */
}
if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
- command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
- ", CID2 0x%2.2" PRIx32
- ", CID1 0x%2.2" PRIx32
- ", CID0 0x%2.2" PRIx32,
- c_cid3, c_cid2, c_cid1, c_cid0);
- command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
- "%2.2x %2.2x %2.2x %2.2x %2.2x",
- (int) c_pid4,
- (int) c_pid3, (int) c_pid2,
- (int) c_pid1, (int) c_pid0);
+ command_print(cmd_ctx,
+ "\t\tCID3 0%2.2x"
+ ", CID2 0%2.2x"
+ ", CID1 0%2.2x"
+ ", CID0 0%2.2x",
+ (int) c_cid3,
+ (int) c_cid2,
+ (int)c_cid1,
+ (int)c_cid0);
+ command_print(cmd_ctx,
+ "\t\tPeripheral ID[4..0] = hex "
+ "%2.2x %2.2x %2.2x %2.2x %2.2x",
+ (int) c_pid4, (int) c_pid3, (int) c_pid2,
+ (int) c_pid1, (int) c_pid0);
/* Part number interpretations are from Cortex
* core specs, the CoreSight components TRM
* (ARM DDI 0314H), and ETM specs; also from
* chip observation (e.g. TI SDTI).
*/
- part_num = c_pid0 & 0xff;
+ part_num = (c_pid0 & 0xff);
part_num |= (c_pid1 & 0x0f) << 8;
switch (part_num) {
case 0x000:
projects / fw / openocd / blobdiff