* Copyright (C) 2013 by Andreas Fritiofson *
* andreas.fritiofson@gmail.com *
* *
+ * Copyright (C) 2019-2021, Ampere Computing LLC *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
uint32_t tar_block_size(uint32_t address)
Return the largest block starting at address that does not cross a tar block size alignment boundary
*/
-static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
+static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, target_addr_t address)
{
return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
}
return ERROR_OK;
}
-static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
+static int mem_ap_setup_tar(struct adiv5_ap *ap, target_addr_t tar)
{
if (!ap->tar_valid || tar != ap->tar_value) {
/* LOG_DEBUG("DAP: Set TAR %x",tar); */
- int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
+ int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, (uint32_t)(tar & 0xffffffffUL));
+ if (retval == ERROR_OK && is_64bit_ap(ap)) {
+ /* See if bits 63:32 of tar is different from last setting */
+ if ((ap->tar_value >> 32) != (tar >> 32))
+ retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR64, (uint32_t)(tar >> 32));
+ }
if (retval != ERROR_OK) {
ap->tar_valid = false;
return retval;
return ERROR_OK;
}
-static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar)
+static int mem_ap_read_tar(struct adiv5_ap *ap, target_addr_t *tar)
{
- int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar);
+ uint32_t lower;
+ uint32_t upper = 0;
+
+ int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, &lower);
+ if (retval == ERROR_OK && is_64bit_ap(ap))
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR64, &upper);
+
if (retval != ERROR_OK) {
ap->tar_valid = false;
return retval;
return retval;
}
+ *tar = (((target_addr_t)upper) << 32) | (target_addr_t)lower;
+
ap->tar_value = *tar;
ap->tar_valid = true;
return ERROR_OK;
*
* @return ERROR_OK if the transaction was properly queued, else a fault code.
*/
-static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
+static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, target_addr_t tar)
{
int retval;
retval = mem_ap_setup_csw(ap, csw);
*
* @return ERROR_OK for success. Otherwise a fault code.
*/
-int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
+int mem_ap_read_u32(struct adiv5_ap *ap, target_addr_t address,
uint32_t *value)
{
int retval;
*/
retval = mem_ap_setup_transfer(ap,
CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
- address & 0xFFFFFFF0);
+ address & 0xFFFFFFFFFFFFFFF0ull);
if (retval != ERROR_OK)
return retval;
* @return ERROR_OK for success; *value holds the result.
* Otherwise a fault code.
*/
-int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
+int mem_ap_read_atomic_u32(struct adiv5_ap *ap, target_addr_t address,
uint32_t *value)
{
int retval;
*
* @return ERROR_OK for success. Otherwise a fault code.
*/
-int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
+int mem_ap_write_u32(struct adiv5_ap *ap, target_addr_t address,
uint32_t value)
{
int retval;
*/
retval = mem_ap_setup_transfer(ap,
CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
- address & 0xFFFFFFF0);
+ address & 0xFFFFFFFFFFFFFFF0ull);
if (retval != ERROR_OK)
return retval;
*
* @return ERROR_OK for success; the data was written. Otherwise a fault code.
*/
-int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
+int mem_ap_write_atomic_u32(struct adiv5_ap *ap, target_addr_t address,
uint32_t value)
{
int retval = mem_ap_write_u32(ap, address, value);
* @return ERROR_OK on success, otherwise an error code.
*/
static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
- uint32_t address, bool addrinc)
+ target_addr_t address, bool addrinc)
{
struct adiv5_dap *dap = ap->dap;
size_t nbytes = size * count;
const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
uint32_t csw_size;
- uint32_t addr_xor;
+ target_addr_t addr_xor;
int retval = ERROR_OK;
/* TI BE-32 Quirks mode:
retval = dap_run(dap);
if (retval != ERROR_OK) {
- uint32_t tar;
+ target_addr_t tar;
if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
- LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
+ LOG_ERROR("Failed to write memory at " TARGET_ADDR_FMT, tar);
else
LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
}
* @return ERROR_OK on success, otherwise an error code.
*/
static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
- uint32_t adr, bool addrinc)
+ target_addr_t adr, bool addrinc)
{
struct adiv5_dap *dap = ap->dap;
size_t nbytes = size * count;
const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
uint32_t csw_size;
- uint32_t address = adr;
+ target_addr_t address = adr;
int retval = ERROR_OK;
/* TI BE-32 Quirks mode:
uint32_t *read_buf = calloc(count, sizeof(uint32_t));
/* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
uint32_t *read_ptr = read_buf;
- if (read_buf == NULL) {
+ if (!read_buf) {
LOG_ERROR("Failed to allocate read buffer");
return ERROR_FAIL;
}
/* If something failed, read TAR to find out how much data was successfully read, so we can
* at least give the caller what we have. */
if (retval != ERROR_OK) {
- uint32_t tar;
+ target_addr_t tar;
if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
/* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
- LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
+ LOG_ERROR("Failed to read memory at " TARGET_ADDR_FMT, tar);
if (nbytes > tar - address)
nbytes = tar - address;
} else {
}
int mem_ap_read_buf(struct adiv5_ap *ap,
- uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
+ uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
{
return mem_ap_read(ap, buffer, size, count, address, true);
}
int mem_ap_write_buf(struct adiv5_ap *ap,
- const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
+ const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
{
return mem_ap_write(ap, buffer, size, count, address, true);
}
int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
- uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
+ uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
{
return mem_ap_read(ap, buffer, size, count, address, false);
}
int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
- const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
+ const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address)
{
return mem_ap_write(ap, buffer, size, count, address, false);
}
int retval;
struct adiv5_dap *dap = ap->dap;
+ /* Set ap->cfg_reg before calling mem_ap_setup_transfer(). */
+ /* mem_ap_setup_transfer() needs to know if the MEM_AP supports LPAE. */
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = dap_run(dap);
+ if (retval != ERROR_OK)
+ return retval;
+
+ ap->cfg_reg = cfg;
ap->tar_valid = false;
ap->csw_value = 0; /* force csw and tar write */
retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
- if (retval != ERROR_OK)
- return retval;
-
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
ap->unaligned_access_bad = dap->ti_be_32_quirks;
LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
- !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
+ !!(cfg & MEM_AP_REG_CFG_LD), !!(cfg & MEM_AP_REG_CFG_LA), !!(cfg & MEM_AP_REG_CFG_BE));
return ERROR_OK;
}
}
int dap_get_debugbase(struct adiv5_ap *ap,
- uint32_t *dbgbase, uint32_t *apid)
+ target_addr_t *dbgbase, uint32_t *apid)
{
struct adiv5_dap *dap = ap->dap;
int retval;
+ uint32_t baseptr_upper, baseptr_lower;
+
+ baseptr_upper = 0;
+
+ if (is_64bit_ap(ap)) {
+ /* Read higher order 32-bits of base address */
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseptr_upper);
+ if (retval != ERROR_OK)
+ return retval;
+ }
- retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseptr_lower);
if (retval != ERROR_OK)
return retval;
retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
if (retval != ERROR_OK)
return retval;
+ *dbgbase = (((target_addr_t)baseptr_upper) << 32) | baseptr_lower;
+
return ERROR_OK;
}
int dap_lookup_cs_component(struct adiv5_ap *ap,
- uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
+ target_addr_t dbgbase, uint8_t type, target_addr_t *addr, int32_t *idx)
{
- uint32_t romentry, entry_offset = 0, component_base, devtype;
+ uint32_t romentry, entry_offset = 0, devtype;
+ target_addr_t component_base;
int retval;
+ dbgbase &= 0xFFFFFFFFFFFFF000ull;
*addr = 0;
do {
- retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
+ retval = mem_ap_read_atomic_u32(ap, dbgbase |
entry_offset, &romentry);
if (retval != ERROR_OK)
return retval;
- component_base = (dbgbase & 0xFFFFF000)
- + (romentry & 0xFFFFF000);
+ component_base = dbgbase + (target_addr_t)(romentry & 0xFFFFF000);
if (romentry & 0x1) {
uint32_t c_cid1;
retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
if (retval != ERROR_OK) {
- LOG_ERROR("Can't read component with base address 0x%" PRIx32
+ LOG_ERROR("Can't read component with base address " TARGET_ADDR_FMT
", the corresponding core might be turned off", component_base);
return retval;
}
return retval;
}
- retval = mem_ap_read_atomic_u32(ap,
- (component_base & 0xfffff000) | 0xfcc,
- &devtype);
+ retval = mem_ap_read_atomic_u32(ap, component_base | 0xfcc, &devtype);
if (retval != ERROR_OK)
return retval;
if ((devtype & 0xff) == type) {
}
}
entry_offset += 4;
- } while (romentry > 0);
+ } while ((romentry > 0) && (entry_offset < 0xf00));
if (!*addr)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
return ERROR_OK;
}
-static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
+static int dap_read_part_id(struct adiv5_ap *ap, target_addr_t component_base, uint32_t *cid, uint64_t *pid)
{
assert((component_base & 0xFFF) == 0);
- assert(ap != NULL && cid != NULL && pid != NULL);
+ assert(ap && cid && pid);
uint32_t cid0, cid1, cid2, cid3;
uint32_t pid0, pid1, pid2, pid3, pid4;
{ 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
{ 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
{ 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
+ { 0x1bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", },
+ { 0x1bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", },
+ { 0x1bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", },
+ { 0x1bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", },
{ 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
{ 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
{ 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
};
static int dap_rom_display(struct command_invocation *cmd,
- struct adiv5_ap *ap, uint32_t dbgbase, int depth)
+ struct adiv5_ap *ap, target_addr_t dbgbase, int depth)
{
int retval;
uint64_t pid;
if (depth)
snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
- uint32_t base_addr = dbgbase & 0xFFFFF000;
- command_print(cmd, "\t\tComponent base address 0x%08" PRIx32, base_addr);
+ target_addr_t base_addr = dbgbase & 0xFFFFFFFFFFFFF000ull;
+ command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, base_addr);
retval = dap_read_part_id(ap, base_addr, &cid, &pid);
if (retval != ERROR_OK) {
/* component may take multiple 4K pages */
uint32_t size = (pid >> 36) & 0xf;
if (size > 0)
- command_print(cmd, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
+ command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, base_addr - 0x1000 * size);
command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, pid);
struct adiv5_ap *ap)
{
int retval;
- uint32_t dbgbase, apid;
+ uint32_t apid;
+ target_addr_t dbgbase;
+ target_addr_t dbgaddr;
uint8_t mem_ap;
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
*/
mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
if (mem_ap) {
- command_print(cmd, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
+ if (is_64bit_ap(ap))
+ dbgaddr = 0xFFFFFFFFFFFFFFFFull;
+ else
+ dbgaddr = 0xFFFFFFFFul;
- if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
+ command_print(cmd, "MEM-AP BASE " TARGET_ADDR_FMT, dbgbase);
+
+ if (dbgbase == dbgaddr || (dbgbase & 0x3) == 0x2) {
command_print(cmd, "\tNo ROM table present");
} else {
if (dbgbase & 0x01)
else
command_print(cmd, "\tROM table in legacy format");
- dap_rom_display(cmd, ap, dbgbase & 0xFFFFF000, 0);
+ dap_rom_display(cmd, ap, dbgbase & 0xFFFFFFFFFFFFF000ull, 0);
}
}
int e;
pc = (struct adiv5_private_config *)target->private_config;
- if (pc == NULL) {
+ if (!pc) {
pc = calloc(1, sizeof(struct adiv5_private_config));
pc->ap_num = DP_APSEL_INVALID;
target->private_config = pc;
int adiv5_verify_config(struct adiv5_private_config *pc)
{
- if (pc == NULL)
+ if (!pc)
return ERROR_FAIL;
- if (pc->dap == NULL)
+ if (!pc->dap)
return ERROR_FAIL;
return ERROR_OK;
COMMAND_HANDLER(dap_baseaddr_command)
{
struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
- uint32_t apsel, baseaddr;
+ uint32_t apsel, baseaddr_lower, baseaddr_upper;
+ struct adiv5_ap *ap;
+ target_addr_t baseaddr;
int retval;
+ baseaddr_upper = 0;
+
switch (CMD_ARGC) {
case 0:
apsel = dap->apsel;
* though they're not common for now. This should
* use the ID register to verify it's a MEM-AP.
*/
- retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
+
+ ap = dap_ap(dap, apsel);
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, &baseaddr_lower);
+
+ if (is_64bit_ap(ap) && retval == ERROR_OK)
+ retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE64, &baseaddr_upper);
if (retval != ERROR_OK)
return retval;
retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
-
- command_print(CMD, "0x%8.8" PRIx32, baseaddr);
+ if (is_64bit_ap(ap)) {
+ baseaddr = (((target_addr_t)baseaddr_upper) << 32) | baseaddr_lower;
+ command_print(CMD, "0x%016" PRIx64, baseaddr);
+ } else
+ command_print(CMD, "0x%08" PRIx32, baseaddr_lower);
return retval;
}
ap->csw_value = value;
break;
case MEM_AP_REG_TAR:
- ap->tar_valid = false; /* invalid, force write */
- retval = mem_ap_setup_tar(ap, value);
+ retval = dap_queue_ap_write(ap, reg, value);
+ if (retval == ERROR_OK)
+ ap->tar_value = (ap->tar_value & ~0xFFFFFFFFull) | value;
+ else {
+ /* To track independent writes to TAR and TAR64, two tar_valid flags */
+ /* should be used. To keep it simple, tar_valid is only invalidated on a */
+ /* write fail. This approach causes a later re-write of the TAR and TAR64 */
+ /* if tar_valid is false. */
+ ap->tar_valid = false;
+ }
+ break;
+ case MEM_AP_REG_TAR64:
+ retval = dap_queue_ap_write(ap, reg, value);
+ if (retval == ERROR_OK)
+ ap->tar_value = (ap->tar_value & 0xFFFFFFFFull) | (((target_addr_t)value) << 32);
+ else {
+ /* See above comment for the MEM_AP_REG_TAR failed write case */
+ ap->tar_valid = false;
+ }
break;
default:
retval = dap_queue_ap_write(ap, reg, value);
projects / fw / openocd / blobdiff