#include "arm9tdmi.h"
#include "target_type.h"
+#include "register.h"
/*
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-static const arm9tdmi_vector_t arm9tdmi_vectors[] =
+enum arm9tdmi_vector_bit
{
+ ARM9TDMI_RESET_VECTOR = 0x01,
+ ARM9TDMI_UNDEF_VECTOR = 0x02,
+ ARM9TDMI_SWI_VECTOR = 0x04,
+ ARM9TDMI_PABT_VECTOR = 0x08,
+ ARM9TDMI_DABT_VECTOR = 0x10,
+ /* BIT(5) reserved -- must be zero */
+ ARM9TDMI_IRQ_VECTOR = 0x40,
+ ARM9TDMI_FIQ_VECTOR = 0x80,
+};
+
+static const struct arm9tdmi_vector {
+ char *name;
+ uint32_t value;
+} arm9tdmi_vectors[] = {
{"reset", ARM9TDMI_RESET_VECTOR},
{"undef", ARM9TDMI_UNDEF_VECTOR},
{"swi", ARM9TDMI_SWI_VECTOR},
{0, 0},
};
-int arm9tdmi_examine_debug_reason(target_t *target)
+int arm9tdmi_examine_debug_reason(struct target *target)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
/* only check the debug reason if we don't know it already */
if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP))
{
- scan_field_t fields[3];
+ struct scan_field fields[3];
uint8_t databus[4];
uint8_t instructionbus[4];
uint8_t debug_reason;
/* put an instruction in the ARM9TDMI pipeline or write the data bus,
* and optionally read data
*/
-int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr,
+int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr,
uint32_t out, uint32_t *in, int sysspeed)
{
int retval = ERROR_OK;
- scan_field_t fields[3];
+ struct scan_field fields[3];
uint8_t out_buf[4];
uint8_t instr_buf[4];
uint8_t sysspeed_buf = 0x0;
}
/* just read data (instruction and data-out = don't care) */
-int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in)
+int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
{
int retval = ERROR_OK;;
- scan_field_t fields[3];
+ struct scan_field fields[3];
jtag_set_end_state(TAP_DRPAUSE);
if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
* the *in pointer points to a buffer where elements of 'size' bytes
* are stored in big (be == 1) or little (be == 0) endianness
*/
-int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info,
+int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
void *in, int size, int be)
{
int retval = ERROR_OK;
- scan_field_t fields[3];
+ struct scan_field fields[3];
jtag_set_end_state(TAP_DRPAUSE);
if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
return ERROR_OK;
}
-static void arm9tdmi_change_to_arm(target_t *target,
+static void arm9tdmi_change_to_arm(struct target *target,
uint32_t *r0, uint32_t *pc)
{
int retval = ERROR_OK;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* save r0 before using it and put system in ARM state
* to allow common handling of ARM and THUMB debugging */
*pc -= 0xc;
}
-void arm9tdmi_read_core_regs(target_t *target,
+void arm9tdmi_read_core_regs(struct target *target,
uint32_t mask, uint32_t* core_regs[16])
{
int i;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* STMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
}
}
-static void arm9tdmi_read_core_regs_target_buffer(target_t *target,
+static void arm9tdmi_read_core_regs_target_buffer(struct target *target,
uint32_t mask, void* buffer, int size)
{
int i;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
uint32_t *buf_u32 = buffer;
uint16_t *buf_u16 = buffer;
}
}
-static void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
+static void arm9tdmi_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* MRS r0, cpsr */
arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
}
-static void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
+static void arm9tdmi_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-static void arm9tdmi_write_xpsr_im8(target_t *target,
+static void arm9tdmi_write_xpsr_im8(struct target *target,
uint8_t xpsr_im, int rot, int spsr)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
}
}
-void arm9tdmi_write_core_regs(target_t *target,
+void arm9tdmi_write_core_regs(struct target *target,
uint32_t mask, uint32_t core_regs[16])
{
int i;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-void arm9tdmi_load_word_regs(target_t *target, uint32_t mask)
+void arm9tdmi_load_word_regs(struct target *target, uint32_t mask)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed load-multiple into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-void arm9tdmi_load_hword_reg(target_t *target, int num)
+void arm9tdmi_load_hword_reg(struct target *target, int num)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed load half-word into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-void arm9tdmi_load_byte_reg(target_t *target, int num)
+void arm9tdmi_load_byte_reg(struct target *target, int num)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed load byte into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-void arm9tdmi_store_word_regs(target_t *target, uint32_t mask)
+void arm9tdmi_store_word_regs(struct target *target, uint32_t mask)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed store-multiple into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-void arm9tdmi_store_hword_reg(target_t *target, int num)
+void arm9tdmi_store_hword_reg(struct target *target, int num)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed store half-word into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-void arm9tdmi_store_byte_reg(target_t *target, int num)
+void arm9tdmi_store_byte_reg(struct target *target, int num)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* put system-speed store byte into the pipeline */
arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-static void arm9tdmi_write_pc(target_t *target, uint32_t pc)
+static void arm9tdmi_write_pc(struct target *target, uint32_t pc)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
}
-void arm9tdmi_branch_resume(target_t *target)
+void arm9tdmi_branch_resume(struct target *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
}
-static void arm9tdmi_branch_resume_thumb(target_t *target)
+static void arm9tdmi_branch_resume_thumb(struct target *target)
{
LOG_DEBUG("-");
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
- reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ struct arm_jtag *jtag_info = &arm7_9->jtag_info;
+ struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
}
-void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc)
+void arm9tdmi_enable_single_step(struct target *target, uint32_t next_pc)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (arm7_9->has_single_step)
{
}
}
-void arm9tdmi_disable_single_step(target_t *target)
+void arm9tdmi_disable_single_step(struct target *target)
{
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
if (arm7_9->has_single_step)
{
}
}
-static void arm9tdmi_build_reg_cache(target_t *target)
+static void arm9tdmi_build_reg_cache(struct target *target)
{
- reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+ struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
armv4_5->core_cache = (*cache_p);
}
-int arm9tdmi_examine(struct target_s *target)
-{
- int retval;
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
-
- if (!target_was_examined(target))
- {
- reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
- reg_cache_t *t;
- /* one extra register (vector catch) */
- t = embeddedice_build_reg_cache(target, arm7_9);
- if (t == NULL)
- return ERROR_FAIL;
- (*cache_p) = t;
- arm7_9->eice_cache = (*cache_p);
-
- if (arm7_9->armv4_5_common.etm)
- {
- arm_jtag_t *jtag_info = &arm7_9->jtag_info;
- (*cache_p)->next = etm_build_reg_cache(target,
- jtag_info, arm7_9->armv4_5_common.etm);
- arm7_9->armv4_5_common.etm->reg_cache = (*cache_p)->next;
- }
- target_set_examined(target);
- }
- if ((retval = embeddedice_setup(target)) != ERROR_OK)
- return retval;
- if ((retval = arm7_9_setup(target)) != ERROR_OK)
- return retval;
- if (arm7_9->armv4_5_common.etm)
- {
- if ((retval = etm_setup(target)) != ERROR_OK)
- return retval;
- }
- return ERROR_OK;
-}
-
-int arm9tdmi_init_target(struct command_context_s *cmd_ctx,
- struct target_s *target)
+int arm9tdmi_init_target(struct command_context *cmd_ctx,
+ struct target *target)
{
arm9tdmi_build_reg_cache(target);
return ERROR_OK;
}
-int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, struct jtag_tap *tap)
+int arm9tdmi_init_arch_info(struct target *target,
+ struct arm7_9_common *arm7_9, struct jtag_tap *tap)
{
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
-
- arm7_9 = &arm9tdmi->arm7_9_common;
- armv4_5 = &arm7_9->armv4_5_common;
-
/* prepare JTAG information for the new target */
arm7_9->jtag_info.tap = tap;
arm7_9->jtag_info.scann_size = 5;
return ERROR_OK;
}
-static int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
+static int arm9tdmi_target_create(struct target *target, Jim_Interp *interp)
{
- arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
+ struct arm7_9_common *arm7_9 = calloc(1,sizeof(struct arm7_9_common));
- arm9tdmi_init_arch_info(target, arm9tdmi, target->tap);
- arm9tdmi->arm7_9_common.armv4_5_common.is_armv4 = true;
+ arm9tdmi_init_arch_info(target, arm7_9, target->tap);
+ arm7_9->armv4_5_common.is_armv4 = true;
return ERROR_OK;
}
COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
{
- target_t *target = get_current_target(cmd_ctx);
- struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
- reg_t *vector_catch;
+ struct target *target = get_current_target(cmd_ctx);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct reg *vector_catch;
uint32_t vector_catch_value;
/* it's uncommon, but some ARM7 chips can support this */
/* get the current setting */
vector_catch_value = buf_get_u32(vector_catch->value, 0, 8);
- if (argc > 0)
+ if (CMD_ARGC > 0)
{
vector_catch_value = 0x0;
if (strcmp(args[0], "all") == 0)
}
else
{
- for (unsigned i = 0; i < argc; i++)
+ for (unsigned i = 0; i < CMD_ARGC; i++)
{
/* go through list of vectors */
unsigned j;
return ERROR_OK;
}
-int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
+int arm9tdmi_register_commands(struct command_context *cmd_ctx)
{
int retval;
- command_t *arm9tdmi_cmd;
+ struct command *arm9tdmi_cmd;
retval = arm7_9_register_commands(cmd_ctx);
arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9",
}
/** Holds methods for ARM9TDMI targets. */
-target_type_t arm9tdmi_target =
+struct target_type arm9tdmi_target =
{
.name = "arm9tdmi",
.read_memory = arm7_9_read_memory,
.write_memory = arm7_9_write_memory,
.bulk_write_memory = arm7_9_bulk_write_memory,
- .checksum_memory = arm7_9_checksum_memory,
- .blank_check_memory = arm7_9_blank_check_memory,
+
+ .checksum_memory = arm_checksum_memory,
+ .blank_check_memory = arm_blank_check_memory,
.run_algorithm = armv4_5_run_algorithm,
.register_commands = arm9tdmi_register_commands,
.target_create = arm9tdmi_target_create,
.init_target = arm9tdmi_init_target,
- .examine = arm9tdmi_examine,
+ .examine = arm7_9_examine,
};
projects / fw / openocd / blobdiff