+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* Copyright (C) 2010 by Drasko DRASKOVIC *
* drasko.draskovic@gmail.com *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
/**
* flag to give info about cache manipulation during debug :
* "0" - cache lines are invalidated "on the fly", for affected addresses.
- * This is prefered from performance point of view.
+ * This is preferred from performance point of view.
* "1" - cache is invalidated and switched off on debug_entry, and switched back on on restore.
* It is kept off during debugging.
*/
static uint8_t arm946e_preserve_cache;
-int arm946e_post_debug_entry(struct target *target);
-void arm946e_pre_restore_context(struct target *target);
+static int arm946e_post_debug_entry(struct target *target);
+static void arm946e_pre_restore_context(struct target *target);
static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *value);
int arm946e_init_arch_info(struct target *target,
return ERROR_OK;
}
+static void arm946e_deinit_target(struct target *target)
+{
+ struct arm *arm = target_to_arm(target);
+ struct arm946e_common *arm946e = target_to_arm946(target);
+
+ arm7_9_deinit(target);
+ arm_free_reg_cache(arm);
+ free(arm946e);
+}
+
static int arm946e_verify_pointer(struct command_invocation *cmd,
struct arm946e_common *arm946e)
{
if (arm946e->common_magic != ARM946E_COMMON_MAGIC) {
- command_print(cmd->ctx, "target is not an ARM946");
+ command_print(cmd, "target is not an ARM946");
return ERROR_TARGET_INVALID;
}
return ERROR_OK;
return csize ? 1 << (12 + (csize-3)) : 0;
}
-uint32_t arm946e_invalidate_whole_dcache(struct target *target)
+static uint32_t arm946e_invalidate_whole_dcache(struct target *target)
{
uint32_t csize = arm946e_cp15_get_csize(target, GET_DCACHE_SIZE);
if (csize == 0)
*/
int nb_idx = (csize / (4*8*NB_CACHE_WAYS)); /* gives nb of lines (indexes) in the cache */
- /* Loop for all segmentde (i.e. ways) */
+ /* Loop for all segments (i.e. ways) */
uint32_t seg;
for (seg = 0; seg < NB_CACHE_WAYS; seg++) {
/* Loop for all indexes */
/* Read dtag */
uint32_t dtag;
- arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag);
+ retval = arm946e_read_cp15(target, 0x16, &dtag);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("ERROR reading dtag");
+ return retval;
+ }
/* Check cache line VALID bit */
if (!(dtag >> 4 & 0x1))
return ERROR_OK;
}
-uint32_t arm946e_invalidate_whole_icache(struct target *target)
+static uint32_t arm946e_invalidate_whole_icache(struct target *target)
{
/* Check cache presence before flushing - avoid undefined behavior */
uint32_t csize = arm946e_cp15_get_csize(target, GET_ICACHE_SIZE);
return ERROR_OK;
}
-int arm946e_post_debug_entry(struct target *target)
+static int arm946e_post_debug_entry(struct target *target)
{
uint32_t ctr_reg = 0x0;
uint32_t retval = ERROR_OK;
/* See if CACHES are enabled, and save that info
* in the context bits, so that arm946e_pre_restore_context() can use them */
- arm946e_read_cp15(target, CP15_CTL, (uint32_t *) &ctr_reg);
+ arm946e_read_cp15(target, CP15_CTL, &ctr_reg);
/* Save control reg in the context */
arm946e->cp15_control_reg = ctr_reg;
return ERROR_OK;
}
-void arm946e_pre_restore_context(struct target *target)
+static void arm946e_pre_restore_context(struct target *target)
{
uint32_t ctr_reg = 0x0;
uint32_t retval;
if (arm946e_preserve_cache) {
struct arm946e_common *arm946e = target_to_arm946(target);
/* Get the contents of the CTR reg */
- arm946e_read_cp15(target, CP15_CTL, (uint32_t *) &ctr_reg);
+ arm946e_read_cp15(target, CP15_CTL, &ctr_reg);
/**
* Read-modify-write CP15 control
} /* if preserve_cache */
}
-uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
+static uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
uint32_t size, uint32_t count)
{
uint32_t cur_addr = 0x0;
}
/* Read dtag */
- arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag);
+ retval = arm946e_read_cp15(target, 0x16, &dtag);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("ERROR reading dtag");
+ return retval;
+ }
/* Check cache line VALID bit */
if (!(dtag >> 4 & 0x1))
return ERROR_OK;
}
-uint32_t arm946e_invalidate_icache(struct target *target, uint32_t address,
+static uint32_t arm946e_invalidate_icache(struct target *target, uint32_t address,
uint32_t size, uint32_t count)
{
uint32_t cur_addr = 0x0;
}
/* Read itag */
- arm946e_read_cp15(target, 0x17, (uint32_t *) &itag);
+ retval = arm946e_read_cp15(target, 0x17, &itag);
+ if (retval != ERROR_OK) {
+ LOG_DEBUG("ERROR reading itag");
+ return retval;
+ }
/* Check cache line VALID bit */
if (!(itag >> 4 & 0x1))
}
/** Writes a buffer, in the specified word size, with current MMU settings. */
-int arm946e_write_memory(struct target *target, target_addr_t address,
+static int arm946e_write_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
int retval;
}
-int arm946e_read_memory(struct target *target, target_addr_t address,
+static int arm946e_read_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
return retval;
if (target->state != TARGET_HALTED) {
- command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+ command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_TARGET_NOT_HALTED;
}
uint32_t value;
retval = arm946e_read_cp15(target, address, &value);
if (retval != ERROR_OK) {
- command_print(CMD_CTX, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
+ command_print(CMD, "%s cp15 reg %" PRIu32 " access failed", target_name(target), address);
return retval;
}
retval = jtag_execute_queue();
return retval;
/* Return value in hex format */
- command_print(CMD_CTX, "0x%08" PRIx32, value);
+ command_print(CMD, "0x%08" PRIx32, value);
} else if (CMD_ARGC == 2) {
uint32_t value;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
retval = arm946e_write_cp15(target, address, value);
if (retval != ERROR_OK) {
- command_print(CMD_CTX, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
+ command_print(CMD, "%s cp15 reg %" PRIu32 " access failed", target_name(target), address);
return retval;
}
if (address == CP15_CTL)
return retval;
if (target->state != TARGET_HALTED) {
- command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+ command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_TARGET_NOT_HALTED;
}
bool bena = ((arm946e->cp15_control_reg & (icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE)) != 0)
&& (arm946e->cp15_control_reg & 0x1);
if (csize == 0)
- command_print(CMD_CTX, "%s-cache absent", icache ? "I" : "D");
+ command_print(CMD, "%s-cache absent", icache ? "I" : "D");
else
- command_print(CMD_CTX, "%s-cache size: %" PRIu32 "K, %s",
+ command_print(CMD, "%s-cache size: %" PRIu32 "K, %s",
icache ? "I" : "D", csize, bena ? "enabled" : "disabled");
return ERROR_OK;
}
/* Do not invalidate or change state, if cache is absent */
if (csize == 0) {
- command_print(CMD_CTX, "%s-cache absent, '%s' operation undefined", icache ? "I" : "D", CMD_ARGV[0]);
+ command_print(CMD, "%s-cache absent, '%s' operation undefined", icache ? "I" : "D", CMD_ARGV[0]);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
.commands = arm946e_command_handlers,
.target_create = arm946e_target_create,
.init_target = arm9tdmi_init_target,
+ .deinit_target = arm946e_deinit_target,
.examine = arm7_9_examine,
.check_reset = arm7_9_check_reset,
};
projects / fw / openocd / blobdiff