return ERROR_OK;
}
+/*
+ * Update cp15_control_reg, saved on debug_entry.
+ */
+static void arm946e_update_cp15_caches(struct target *target, uint32_t value)
+{
+ struct arm946e_common *arm946e = target_to_arm946(target);
+ arm946e->cp15_control_reg = (arm946e->cp15_control_reg & ~(CP15_CTL_DCACHE|CP15_CTL_ICACHE))
+ | (value & (CP15_CTL_DCACHE|CP15_CTL_ICACHE));
+}
+
/*
* REVISIT: The "read_cp15" and "write_cp15" commands could hook up
* to eventual mrc() and mcr() routines ... the reg_addr values being
return ERROR_OK;
}
-uint32_t arm946e_invalidate_whole_dcache(struct target *target)
-{
-
- uint32_t csize = 0;
- uint32_t shift = 0;
- uint32_t cp15_idx, seg, dtag;
- int nb_idx, idx = 0;
- int retval;
-
- /* Get cache type */
- arm946e_read_cp15(target, 0x01, (uint32_t *) &csize);
+#define GET_ICACHE_SIZE 6
+#define GET_DCACHE_SIZE 18
- csize = (csize >> 18) & 0x0F;
+/*
+ * \param target struct target pointer
+ * \param idsel select GET_ICACHE_SIZE or GET_DCACHE_SIZE
+ * \returns cache size, given in bytes
+ */
+static uint32_t arm946e_cp15_get_csize(struct target *target, int idsel)
+{
+ struct arm946e_common *arm946e = target_to_arm946(target);
+ uint32_t csize = arm946e->cp15_cache_info;
+ if (csize == 0) {
+ if (arm946e_read_cp15(target, 0x01, &csize) == ERROR_OK)
+ arm946e->cp15_cache_info = csize;
+ }
+ if (csize & (1<<(idsel-4))) /* cache absent */
+ return 0;
+ csize = (csize >> idsel) & 0x0F;
+ return csize ? 1 << (12 + (csize-3)) : 0;
+}
+uint32_t arm946e_invalidate_whole_dcache(struct target *target)
+{
+ uint32_t csize = arm946e_cp15_get_csize(target, GET_DCACHE_SIZE);
if (csize == 0)
- shift = 0;
- else
- shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- /* Cache size, given in bytes */
- csize = 1 << (12 + shift);
- /* One line (index) is 32 bytes (8 words) long */
- nb_idx = (csize / 32); /* gives nb of lines (indexes) in the cache */
+ /* One line (index) is 32 bytes (8 words) long, 4-way assoc
+ * ARM DDI 0201D, Section 3.3.5
+ */
+ int nb_idx = (csize / (4*8*NB_CACHE_WAYS)); /* gives nb of lines (indexes) in the cache */
/* Loop for all segmentde (i.e. ways) */
+ uint32_t seg;
for (seg = 0; seg < NB_CACHE_WAYS; seg++) {
/* Loop for all indexes */
+ int idx;
for (idx = 0; idx < nb_idx; idx++) {
/* Form and write cp15 index (segment + line idx) */
- cp15_idx = seg << 30 | idx << 5;
- retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
+ uint32_t cp15_idx = seg << 30 | idx << 5;
+ int retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR writing index");
return retval;
}
/* Read dtag */
+ uint32_t dtag;
arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag);
/* Check cache line VALID bit */
uint32_t arm946e_invalidate_whole_icache(struct target *target)
{
- int retval;
+ /* Check cache presence before flushing - avoid undefined behavior */
+ uint32_t csize = arm946e_cp15_get_csize(target, GET_ICACHE_SIZE);
+ if (csize == 0)
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
LOG_DEBUG("FLUSHING I$");
-
/**
* Invalidate (flush) I$
* mcr 15, 0, r0, cr7, cr5, {0}
*/
- retval = arm946e_write_cp15(target, 0x0f, 0x1);
+ int retval = arm946e_write_cp15(target, 0x0f, 0x1);
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR flushing I$");
return retval;
uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
uint32_t size, uint32_t count)
{
- uint32_t csize = 0x0;
- uint32_t shift = 0;
uint32_t cur_addr = 0x0;
uint32_t cp15_idx, set, way, dtag;
uint32_t i = 0;
for (i = 0; i < count*size; i++) {
cur_addr = address + i;
- /* Get cache type */
- arm946e_read_cp15(target, 0x01, (uint32_t *) &csize);
-
- /* Conclude cache size to find number of lines */
- csize = (csize >> 18) & 0x0F;
-
- if (csize == 0)
- shift = 0;
- else
- shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */
-
- csize = 1 << (12 + shift);
set = (cur_addr >> 5) & 0xff; /* set field is 8 bits long */
return ERROR_OK;
}
+static int jim_arm946e_cp15(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
+{
+ /* one or two arguments, access a single register (write if second argument is given) */
+ if (argc < 2 || argc > 3) {
+ Jim_WrongNumArgs(interp, 1, argv, "addr [value]");
+ return JIM_ERR;
+ }
+
+ struct command_context *cmd_ctx = current_command_context(interp);
+ assert(cmd_ctx != NULL);
+
+ struct target *target = get_current_target(cmd_ctx);
+ if (target == NULL) {
+ LOG_ERROR("arm946e: no current target");
+ return JIM_ERR;
+ }
+
+ struct arm946e_common *arm946e = target_to_arm946(target);
+ int retval = arm946e_verify_pointer(cmd_ctx, arm946e);
+ if (retval != ERROR_OK)
+ return JIM_ERR;
+
+ if (target->state != TARGET_HALTED) {
+ command_print(cmd_ctx, "target %s must be stopped for \"cp15\" command", target_name(target));
+ return JIM_ERR;
+ }
+
+ long l;
+ uint32_t address;
+ retval = Jim_GetLong(interp, argv[1], &l);
+ address = l;
+ if (JIM_OK != retval)
+ return retval;
-COMMAND_HANDLER(arm946e_handle_cp15_command)
+ if (argc == 2) {
+ uint32_t value;
+ retval = arm946e_read_cp15(target, address, &value);
+ if (retval != ERROR_OK) {
+ command_print(cmd_ctx, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
+ return JIM_ERR;
+ }
+ retval = jtag_execute_queue();
+ if (retval != ERROR_OK)
+ return JIM_ERR;
+ char buf[20];
+ sprintf(buf, "0x%08x", value);
+ /* Return value in hex format */
+ Jim_SetResultString(interp, buf, -1);
+ } else if (argc == 3) {
+ uint32_t value;
+ retval = Jim_GetLong(interp, argv[2], &l);
+ value = l;
+ if (JIM_OK != retval)
+ return retval;
+ retval = arm946e_write_cp15(target, address, value);
+ if (retval != ERROR_OK) {
+ command_print(cmd_ctx, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
+ return JIM_ERR;
+ }
+ if (address == CP15_CTL)
+ arm946e_update_cp15_caches(target, value);
+ }
+
+ return JIM_OK;
+}
+
+COMMAND_HANDLER(arm946e_handle_idcache)
{
+ if (CMD_ARGC > 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
int retval;
struct target *target = get_current_target(CMD_CTX);
struct arm946e_common *arm946e = target_to_arm946(target);
if (target->state != TARGET_HALTED) {
command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ bool icache = (strcmp(CMD_NAME, "icache") == 0);
+ uint32_t csize = arm946e_cp15_get_csize(target, icache ? GET_ICACHE_SIZE : GET_DCACHE_SIZE) / 1024;
+ if (CMD_ARGC == 0) {
+ bool bena = ((arm946e->cp15_control_reg & (icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE)) != 0)
+ && (arm946e->cp15_control_reg & 0x1);
+ if (csize == 0)
+ command_print(CMD_CTX, "%s-cache absent", icache ? "I" : "D");
+ else
+ command_print(CMD_CTX, "%s-cache size: %dK, %s", icache ? "I" : "D", csize, bena ? "enabled" : "disabled");
return ERROR_OK;
}
- /* one or more argument, access a single register (write if second argument is given */
- if (CMD_ARGC >= 1) {
- uint32_t address;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
+ bool flush = false;
+ bool enable = false;
+ retval = command_parse_bool_arg(CMD_ARGV[0], &enable);
+ if (retval == ERROR_COMMAND_SYNTAX_ERROR) {
+ if (strcmp(CMD_ARGV[0], "flush") == 0) {
+ flush = true;
+ retval = ERROR_OK;
+ } else
+ return retval;
+ }
- if (CMD_ARGC == 1) {
- uint32_t value;
- retval = arm946e_read_cp15(target, address, &value);
- if (retval != ERROR_OK) {
- command_print(CMD_CTX, "couldn't access reg %" PRIi32, address);
- return ERROR_OK;
- }
- retval = jtag_execute_queue();
- if (retval != ERROR_OK)
- return retval;
+ /* Do not invalidate or change state, if cache is absent */
+ if (csize == 0) {
+ command_print(CMD_CTX, "%s-cache absent, '%s' operation undefined", icache ? "I" : "D", CMD_ARGV[0]);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
- command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, address, value);
- } else if (CMD_ARGC == 2) {
- uint32_t value;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
- retval = arm946e_write_cp15(target, address, value);
- if (retval != ERROR_OK) {
- command_print(CMD_CTX, "couldn't access reg %" PRIi32, address);
- return ERROR_OK;
- }
- command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, address, value);
- }
+ /* NOTE: flushing entire cache will not preserve lock-down cache regions */
+ if (icache) {
+ if ((arm946e->cp15_control_reg & CP15_CTL_ICACHE) && !enable)
+ retval = arm946e_invalidate_whole_icache(target);
+ } else {
+ if ((arm946e->cp15_control_reg & CP15_CTL_DCACHE) && !enable)
+ retval = arm946e_invalidate_whole_dcache(target);
}
+ if (retval != ERROR_OK || flush)
+ return retval;
+
+ uint32_t value;
+ retval = arm946e_read_cp15(target, CP15_CTL, &value);
+ if (retval != ERROR_OK)
+ return retval;
+
+ uint32_t vnew = value;
+ uint32_t cmask = icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE;
+ if (enable) {
+ if ((value & 0x1) == 0)
+ LOG_WARNING("arm946e: MPU must be enabled for cache to operate");
+ vnew |= cmask;
+ } else
+ vnew &= ~cmask;
+
+ if (vnew == value)
+ return ERROR_OK;
+
+ retval = arm946e_write_cp15(target, CP15_CTL, vnew);
+ if (retval != ERROR_OK)
+ return retval;
+
+ arm946e_update_cp15_caches(target, vnew);
return ERROR_OK;
}
static const struct command_registration arm946e_exec_command_handlers[] = {
{
.name = "cp15",
- .handler = arm946e_handle_cp15_command,
+ .jim_handler = jim_arm946e_cp15,
.mode = COMMAND_EXEC,
.usage = "regnum [value]",
- .help = "display/modify cp15 register",
+ .help = "read/modify cp15 register",
+ },
+ {
+ .name = "icache",
+ .handler = arm946e_handle_idcache,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable'|'flush']",
+ .help = "I-cache info and operations",
+ },
+ {
+ .name = "dcache",
+ .handler = arm946e_handle_idcache,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable'|'flush']",
+ .help = "D-cache info and operations",
},
COMMAND_REGISTRATION_DONE
};
projects / fw / openocd / blobdiff